summaryrefslogtreecommitdiffstats
path: root/llvm/test/CodeGen/ARM/fp16-instructions.ll
Commit message (Expand)AuthorAgeFilesLines
* [SchedModel] Fix for read advance cycles with implicit pseudo operands.Jonas Paulsson2018-10-301-2/+2
* Relax fast register allocator related test cases; NFCMatthias Braun2018-10-291-1/+1
* [DAG] propagate FMF for all FPMathOperatorsSanjay Patel2018-05-151-1/+1
* [ARM] Add some missing FP16 VSEL test casesSjoerd Meijer2018-04-191-8/+83
* [ARM] FP16 vmaxnm/vminnm scalar instructionsSjoerd Meijer2018-04-131-1/+6
* [ARM] FP16 VSEL codegenSjoerd Meijer2018-04-111-12/+142
* [ARM] FP16 codegen support for VSELSjoerd Meijer2018-03-161-1/+39
* [ARM] Lower BR_CC for f16Sjoerd Meijer2018-02-201-1/+31
* [ARM] f16 vcmp fixesSjoerd Meijer2018-02-151-24/+50
* [ARM] f16 stack spill/reloadsSjoerd Meijer2018-02-141-0/+26
* [Thumb] Handle addressing mode AddrMode5FP16Sjoerd Meijer2018-02-131-0/+24
* [ARM] FP16 mov imm patternSjoerd Meijer2018-02-071-0/+13
* [ARM] f16 conversionsSjoerd Meijer2018-02-061-0/+45
* [ARM] Armv8.2-A FP16 code generation (part 3/3)Sjoerd Meijer2018-02-061-8/+566
* [ARM] FullFP16 LowerReturn FixSjoerd Meijer2018-02-011-8/+21
* [ARM] Armv8.2-A FP16 code generation (part 2/3)Sjoerd Meijer2018-01-311-9/+5
* [ARM] Armv8.2-A FP16 code generation (part 1/3)Sjoerd Meijer2018-01-261-0/+72
OpenPOWER on IntegriCloud