Commit message (Collapse) | Author | Age | Files | Lines | |
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* | [ARM] Regenerate cttz tests | Simon Pilgrim | 2018-10-14 | 1 | -136/+283 |
| | | | | | | Improve codegen view as part of PR32655 llvm-svn: 344479 | ||||
* | [ARM] Make -mcpu=generic schedule for an in-order core (Cortex-A8). | Kristof Beyls | 2017-06-28 | 1 | -32/+32 |
| | | | | | | | | | | | | | | | | The benchmarking summarized in http://lists.llvm.org/pipermail/llvm-dev/2017-May/113525.html showed this is beneficial for a wide range of cores. As is to be expected, quite a few small adaptations are needed to the regressions tests, as the difference in scheduling results in: - Quite a few small instruction schedule differences. - A few changes in register allocation decisions caused by different instruction schedules. - A few changes in IfConversion decisions, due to a difference in instruction schedule and/or the estimated cost of a branch mispredict. llvm-svn: 306514 | ||||
* | ARM: Fix cttz expansion on vector types. | Logan Chien | 2015-07-13 | 1 | -0/+383 |
The 64/128-bit vector types are legal if NEON instructions are available. However, there was no matching patterns for @llvm.cttz.*() intrinsics and result in fatal error. This commit fixes the problem by lowering cttz to: a. ctpop((x & -x) - 1) b. width - ctlz(x & -x) - 1 llvm-svn: 242037 |