summaryrefslogtreecommitdiffstats
path: root/llvm/test/CodeGen/ARM/build-attributes.ll
Commit message (Collapse)AuthorAgeFilesLines
...
* [ARM] Add missing M/R class CPUsBradley Smith2015-02-181-0/+170
| | | | | | | | | | | | Add some of the missing M and R class Cortex CPUs, namely: Cortex-M0+ (called Cortex-M0plus for GCC compatibility) Cortex-M1 SC000 SC300 Cortex-R5 llvm-svn: 229660
* [ARM] Add armv6s[-]m as an alias to armv6[-]mBradley Smith2015-02-101-0/+4
| | | | llvm-svn: 228696
* Adding support to LLVM for targeting Cortex-A72Renato Golin2015-02-041-0/+36
| | | | | | | | | | Currently, Cortex-A72 is modelled as an Cortex-A57 except the fp load balancing pass isn't enabled for Cortex-A72 as it's not profitable to have it enabled for this core. Patch by Ranjeet Singh. llvm-svn: 228140
* Add a missing Tag_DIV_use test for Cortex-M7.Charlie Turner2015-01-291-0/+1
| | | | llvm-svn: 227429
* [ARM] Add missing Tag_DIV_use tests.Charlie Turner2015-01-071-0/+8
| | | | llvm-svn: 225348
* Emit the build attribute Tag_conformance.Charlie Turner2015-01-051-0/+1
| | | | | | | | | | | Claim conformance to version 2.09 of the ARM ABI. This build attribute must be emitted first amongst the build attributes when written to an object file. This is to simplify conformance detection by consumers. Change-Id: If9eddcfc416bc9ad6e5cc8cdcb05d0031af7657e llvm-svn: 225166
* Emit Tag_ABI_FP_16bit_format build attribute.Charlie Turner2014-12-121-0/+21
| | | | | | | | | | | | | The __fp16 type is unconditionally exposed. Since -mfp16-format is not yet supported, there is not a user switch to change this behaviour. This build attribute should capture the default behaviour of the compiler, which is to expose the IEEE 754 version of __fp16. When -mfp16-format is emitted, that will be the way to control the value of this build attribute. Change-Id: I8a46641ff0fd2ef8ad0af5f482a6d1af2ac3f6b0 llvm-svn: 224115
* Add missing FP build attribute tests.Charlie Turner2014-12-051-28/+148
| | | | | | | | | | | | | | | | | | | | | The test file test/CodeGen/ARM/build-attributes.ll was missing several floating-point build attribute tests. The intention of this commit is that for each CPU / architecture currently tested, there are now tests that make sure the following attributes are sufficiently checked, * Tag_ABI_FP_rounding * Tag_ABI_FP_denormal * Tag_ABI_FP_exceptions * Tag_ABI_FP_user_exceptions * Tag_ABI_FP_number_model Also in this commit, the -unsafe-fp-math flag has been augmented with the full suite of flags Clang sends to LLVM when you pass -ffast-math to Clang. That is, `-unsafe-fp-math' has been changed to `-enable-unsafe-fp-math -disable-fp-elim -enable-no-infs-fp-math -enable-no-nans-fp-math -fp-contract=fast' Change-Id: I35d766076bcbbf09021021c0a534bf8bf9a32dfc llvm-svn: 223454
* Emit ABI_FP_rounding attribute.Charlie Turner2014-12-031-0/+22
| | | | | | | | | | | | LLVM understands a -enable-sign-dependent-rounding-fp-math codegen option. When the user has specified this option, the Tag_ABI_FP_rounding attribute should be emitted with value 1. This option currently does not appear to disable transformations and optimizations that assume default floating point rounding behavior, AFAICT, but the intention should be recorded in the build attributes, regardless of what the compiler actually does with the intention. Change-Id: If838578df3dc652b6f2796b8d152545674bcb30e llvm-svn: 223218
* Add tests for default value of Tag_ABI_FP_rounding.Charlie Turner2014-12-031-0/+48
| | | | | Change-Id: I051866d073fc6ce87ce3e693a3762da6d81f4393 llvm-svn: 223217
* Emit Tag_ABI_FP_denormal correctly in fast-math mode.Charlie Turner2014-12-021-44/+227
| | | | | | | | | | | | | | | | | | | | The default ARM floating-point mode does not support IEEE 754 mode exactly. Of relevance to this patch is that input denormals are flushed to zero. The way in which they're flushed to zero depends on the architecture, * For VFPv2, it is implementation defined as to whether the sign of zero is preserved. * For VFPv3 and above, the sign of zero is always preserved when a denormal is flushed to zero. When FP support has been disabled, the strategy taken by this patch is to assume the software support will mirror the behaviour of the hardware support for the target *if it existed*. That is, for architectures which can only have VFPv2, it is assumed the software will flush to positive zero. For later architectures it is assumed the software will flush to zero preserving sign. Change-Id: Icc5928633ba222a4ba3ca8c0df44a440445865fd llvm-svn: 223110
* Remove the cortex-a9-mp CPU.Charlie Turner2014-11-031-20/+2
| | | | | | | | | | | | | | | | | | This CPU definition is redundant. The Cortex-A9 is defined as supporting multiprocessing extensions. Remove its definition and update appropriate tests. LLVM defines both a cortex-a9 CPU and a cortex-a9-mp CPU. The only difference between the two CPU definitions in ARM.td is that cortex-a9-mp contains the feature FeatureMP for multiprocessing extensions. This is redundant since the Cortex-A9 is defined as having multiprocessing extensions in the TRMs. armcc also defines the Cortex-A9 as having multiprocessing extensions by default. Change-Id: Ifcadaa6c322be0a33d9d2a39cfdd7da1d75981a7 llvm-svn: 221166
* ARM: test default values for TAG_CPU_unaligned_access attribute.Tim Northover2014-10-301-0/+9
| | | | | | | | | It should be on for every target that supports unaligned accesses (e.g. not v6m). Patch by Charlie Turner. llvm-svn: 220912
* Adds support for the Cortex-A17 to the ARM backendRenato Golin2014-10-131-0/+32
| | | | | | Patch by Matthew Wahab. llvm-svn: 219606
* Emit unaligned access build attribute for ARMRenato Golin2014-10-081-0/+28
| | | | | | Patch by Charlie Turner. llvm-svn: 219301
* [ARM] Add support for Cortex-M7, FPv5-SP and FPv5-DP (LLVM)Oliver Stannard2014-10-011-0/+23
| | | | | | | | | The Cortex-M7 has 3 options for its FPU: none, FPv5-SP-D16 and FPv5-DP-D16. FPv5 has the same instructions as FP-ARMv8, so it can be modelled using the same target feature, and all double-precision operations are already disabled by the fp-only-sp target features. llvm-svn: 218747
* [ARM] Emit ABI_PCS_R9_use build attribute.Amara Emerson2014-07-251-0/+5
| | | | | | | | Patch by Ben Foster! Differential Revision: http://reviews.llvm.org/D4657 llvm-svn: 213944
* [ARM] Emit correct build attributes for the relocation models.Amara Emerson2014-05-271-0/+10
| | | | | | Patch by Asiri Rathnayake. llvm-svn: 209656
* Fix broken CHECK linesNico Rieck2014-02-161-3/+3
| | | | llvm-svn: 201479
* [ARM] Do not generate Tag_DIV_use=AllowDIVExt when hardware div is ↵Artyom Skrobov2014-01-201-5/+23
| | | | | | non-optional: it should have the default value of AllowDIVIfExists llvm-svn: 199638
* ARM: update build attributes for ABI r2.09Saleem Abdulrasool2014-01-191-1/+1
| | | | | | | Update names for the names as per the current ABI errata. Mark deprecated tags as such. llvm-svn: 199576
* Move the xscale build attribute test to the proper place and remove the old one.Amara Emerson2014-01-161-0/+5
| | | | | | The encoding of build attributes is already tested in CodeGen/ARM/build-attributes-encoding.s llvm-svn: 199393
* Must not produce Tag_CPU_arch_profile for pre-ARMv7 cores (e.g. cortex-m0)Artyom Skrobov2014-01-101-2/+2
| | | | llvm-svn: 198945
* [ARM] Enable FeatureMP for Cortex-A5 by default.Amara Emerson2013-11-251-1/+44
| | | | | | Patch by Oliver Stannard. llvm-svn: 195640
* Add support for Cortex-A12.Richard Barton2013-11-221-0/+32
| | | | | | Patch by Oliver Stannard! llvm-svn: 195448
* [ARM] add the overlooked tests for Cortex-A7 build attributesArtyom Skrobov2013-11-211-0/+360
llvm-svn: 195365
OpenPOWER on IntegriCloud