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| author | Oliver Stannard <oliver.stannard@arm.com> | 2014-10-01 09:02:17 +0000 |
|---|---|---|
| committer | Oliver Stannard <oliver.stannard@arm.com> | 2014-10-01 09:02:17 +0000 |
| commit | 37e4daab05c9fd2848e0cb55f6e39e9697745b3d (patch) | |
| tree | ebaa61a77b1f51d56719fcd27e87105e43c6d48a /llvm/test/CodeGen/ARM/build-attributes.ll | |
| parent | 79dc4420f0106dbc466f00d806484adc9aa8c630 (diff) | |
| download | bcm5719-llvm-37e4daab05c9fd2848e0cb55f6e39e9697745b3d.tar.gz bcm5719-llvm-37e4daab05c9fd2848e0cb55f6e39e9697745b3d.zip | |
[ARM] Add support for Cortex-M7, FPv5-SP and FPv5-DP (LLVM)
The Cortex-M7 has 3 options for its FPU: none, FPv5-SP-D16 and
FPv5-DP-D16. FPv5 has the same instructions as FP-ARMv8, so it can be
modelled using the same target feature, and all double-precision
operations are already disabled by the fp-only-sp target features.
llvm-svn: 218747
Diffstat (limited to 'llvm/test/CodeGen/ARM/build-attributes.ll')
| -rw-r--r-- | llvm/test/CodeGen/ARM/build-attributes.ll | 23 |
1 files changed, 23 insertions, 0 deletions
diff --git a/llvm/test/CodeGen/ARM/build-attributes.ll b/llvm/test/CodeGen/ARM/build-attributes.ll index a4b77c80c10..4243fa4efbd 100644 --- a/llvm/test/CodeGen/ARM/build-attributes.ll +++ b/llvm/test/CodeGen/ARM/build-attributes.ll @@ -26,6 +26,9 @@ ; RUN: llc < %s -mtriple=thumbv7m-linux-gnueabi -mcpu=cortex-m3 | FileCheck %s --check-prefix=CORTEX-M3 ; RUN: llc < %s -mtriple=thumbv7m-linux-gnueabi -mcpu=cortex-m4 -float-abi=soft | FileCheck %s --check-prefix=CORTEX-M4-SOFT ; RUN: llc < %s -mtriple=thumbv7m-linux-gnueabi -mcpu=cortex-m4 -float-abi=hard | FileCheck %s --check-prefix=CORTEX-M4-HARD +; RUN: llc < %s -mtriple=thumbv7em-linux-gnueabi -mcpu=cortex-m7 -mattr=-vfp2 | FileCheck %s --check-prefix=CORTEX-M7 --check-prefix=CORTEX-M7-SOFT +; RUN: llc < %s -mtriple=thumbv7em-linux-gnueabi -mcpu=cortex-m7 -mattr=+fp-only-sp | FileCheck %s --check-prefix=CORTEX-M7 --check-prefix=CORTEX-M7-SINGLE +; RUN: llc < %s -mtriple=thumbv7em-linux-gnueabi -mcpu=cortex-m7 | FileCheck %s --check-prefix=CORTEX-M7 --check-prefix=CORTEX-M7-DOUBLE ; RUN: llc < %s -mtriple=armv7r-linux-gnueabi -mcpu=cortex-r5 | FileCheck %s --check-prefix=CORTEX-R5 ; RUN: llc < %s -mtriple=armv8-linux-gnueabi -mcpu=cortex-a53 | FileCheck %s --check-prefix=CORTEX-A53 ; RUN: llc < %s -mtriple=armv8-linux-gnueabi -mcpu=cortex-a57 | FileCheck %s --check-prefix=CORTEX-A57 @@ -410,6 +413,26 @@ ; CORTEX-M4-HARD-NOT: .eabi_attribute 44 ; CORTEX-M4-HARD-NOT: .eabi_attribute 68 +; CORTEX-M7: .cpu cortex-m7 +; CORTEX-M7: .eabi_attribute 6, 13 +; CORTEX-M7: .eabi_attribute 7, 77 +; CORTEX-M7: .eabi_attribute 8, 0 +; CORTEX-M7: .eabi_attribute 9, 2 +; CORTEX-M7-SOFT-NOT: .fpu +; CORTEX-M7-SINGLE: .fpu fpv5-d16 +; CORTEX-M7-DOUBLE: .fpu fpv5-d16 +; CORTEX-M7: .eabi_attribute 17, 1 +; CORTEX-M7: .eabi_attribute 20, 1 +; CORTEX-M7: .eabi_attribute 21, 1 +; CORTEX-M7: .eabi_attribute 23, 3 +; CORTEX-M7: .eabi_attribute 24, 1 +; CORTEX-M7: .eabi_attribute 25, 1 +; CORTEX-M7-SOFT-NOT: .eabi_attribute 27 +; CORTEX-M7-SINGLE: .eabi_attribute 27, 1 +; CORTEX-M7-DOUBLE-NOT: .eabi_attribute 27 +; CORTEX-M7: .eabi_attribute 36, 1 +; CORTEX-M7: .eabi_attribute 14, 0 + ; CORTEX-R5: .cpu cortex-r5 ; CORTEX-R5: .eabi_attribute 6, 10 ; CORTEX-R5: .eabi_attribute 7, 82 |
