Commit message (Collapse) | Author | Age | Files | Lines | |
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* | [AMDGPU] Fix SGPR fixing through SCC chaining | Michael Liao | 2019-03-15 | 1 | -0/+14 |
| | | | | | | | | | | | | | | | | | | Summary: - During the fixing of SGPR copying from VGPR, ensure users of SCC is properly propagated, i.e. * only propagate through live def of SCC, * skip the SCC-def inst itself, and * stop the propagation on the other SCC-def inst after checking its SCC-use first. Subscribers: arsenm, kzhuravl, jvesely, wdng, nhaehnle, yaxunl, dstuttard, tpr, t-tye, hiraditya, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D59362 llvm-svn: 356258 | ||||
* | AMDGPU: Use gfx9 carry-less add/sub instructions | Matt Arsenault | 2017-11-30 | 1 | -0/+1 |
| | | | | llvm-svn: 319491 | ||||
* | [AMDGPU] New 64 bit div/rem expansion | Stanislav Mekhanoshin | 2017-10-06 | 1 | -66/+12 |
| | | | | | | | | | | | Old expansion was 20 VGPRs, 78 SGPRs and ~380 instructions. This expansion is 11 VGPRs, 12 SGPRs and ~120 instructions. Passes OpenCL conformance test_integer_ops quick_[u]long_math Differential Revision: https://reviews.llvm.org/D38607 llvm-svn: 315081 | ||||
* | AMDGPU: Mark all unspecified CC functions in tests as amdgpu_kernel | Matt Arsenault | 2017-03-21 | 1 | -6/+6 |
| | | | | | | | | | | | | Currently the default C calling convention functions are treated the same as compute kernels. Make this explicit so the default calling convention can be changed to a non-kernel. Converted with perl -pi -e 's/define void/define amdgpu_kernel void/' on the relevant test directories (and undoing in one place that actually wanted a non-kernel). llvm-svn: 298444 | ||||
* | Enable FeatureFlatForGlobal on Volcanic Islands | Matt Arsenault | 2017-01-24 | 1 | -1/+1 |
| | | | | | | | | | | | This switches to the workaround that HSA defaults to for the mesa path. This should be applied to the 4.0 branch. Patch by Vedran Miletić <vedran@miletic.net> llvm-svn: 292982 | ||||
* | AMDGPU: Fix high bits after division optimization | Matt Arsenault | 2016-05-21 | 1 | -9/+9 |
| | | | | | | | This is essentially doing a 24-bit signed division with FP. We need to truncate to the N bit result. llvm-svn: 270305 | ||||
* | R600 -> AMDGPU rename | Tom Stellard | 2015-06-13 | 1 | -0/+223 |
llvm-svn: 239657 |