summaryrefslogtreecommitdiffstats
path: root/llvm/test/CodeGen/AMDGPU/udivrem64.ll
Commit message (Collapse)AuthorAgeFilesLines
* [AMDGPU] Fix SGPR fixing through SCC chainingMichael Liao2019-03-151-0/+14
| | | | | | | | | | | | | | | | | | Summary: - During the fixing of SGPR copying from VGPR, ensure users of SCC is properly propagated, i.e. * only propagate through live def of SCC, * skip the SCC-def inst itself, and * stop the propagation on the other SCC-def inst after checking its SCC-use first. Subscribers: arsenm, kzhuravl, jvesely, wdng, nhaehnle, yaxunl, dstuttard, tpr, t-tye, hiraditya, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D59362 llvm-svn: 356258
* AMDGPU: Use gfx9 carry-less add/sub instructionsMatt Arsenault2017-11-301-0/+1
| | | | llvm-svn: 319491
* [AMDGPU] New 64 bit div/rem expansionStanislav Mekhanoshin2017-10-061-66/+12
| | | | | | | | | | | Old expansion was 20 VGPRs, 78 SGPRs and ~380 instructions. This expansion is 11 VGPRs, 12 SGPRs and ~120 instructions. Passes OpenCL conformance test_integer_ops quick_[u]long_math Differential Revision: https://reviews.llvm.org/D38607 llvm-svn: 315081
* AMDGPU: Mark all unspecified CC functions in tests as amdgpu_kernelMatt Arsenault2017-03-211-6/+6
| | | | | | | | | | | | Currently the default C calling convention functions are treated the same as compute kernels. Make this explicit so the default calling convention can be changed to a non-kernel. Converted with perl -pi -e 's/define void/define amdgpu_kernel void/' on the relevant test directories (and undoing in one place that actually wanted a non-kernel). llvm-svn: 298444
* Enable FeatureFlatForGlobal on Volcanic IslandsMatt Arsenault2017-01-241-1/+1
| | | | | | | | | | | This switches to the workaround that HSA defaults to for the mesa path. This should be applied to the 4.0 branch. Patch by Vedran Miletić <vedran@miletic.net> llvm-svn: 292982
* AMDGPU: Fix high bits after division optimizationMatt Arsenault2016-05-211-9/+9
| | | | | | | This is essentially doing a 24-bit signed division with FP. We need to truncate to the N bit result. llvm-svn: 270305
* R600 -> AMDGPU renameTom Stellard2015-06-131-0/+223
llvm-svn: 239657
OpenPOWER on IntegriCloud