| Commit message (Collapse) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | [codegen,amdgpu] Enhance MIR DIE and re-arrange it for AMDGPU. | Michael Liao | 2020-01-14 | 1 | -1/+1 |
| | | | | | | | | | | | | | | | | | | | | Summary: - `dead-mi-elimination` assumes MIR in the SSA form and cannot be arranged after phi elimination or DeSSA. It's enhanced to handle the dead register definition by skipping use check on it. Once a register def is `dead`, all its uses, if any, should be `undef`. - Re-arrange the DIE in RA phase for AMDGPU by placing it directly after `detect-dead-lanes`. - Many relevant tests are refined due to different register assignment. Reviewers: rampitec, qcolombet, sunfish Subscribers: arsenm, kzhuravl, jvesely, wdng, nhaehnle, yaxunl, dstuttard, tpr, t-tye, hiraditya, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D72709 | ||||
| * | [AMDGPU] Fix bundle scheduling | Stanislav Mekhanoshin | 2020-01-09 | 1 | -1/+1 |
| | | | | | | | | Bundles coming to scheduler considered free, i.e. zero latency. Fixed. Differential Revision: https://reviews.llvm.org/D72487 | ||||
| * | [AMDGPU] Reserve all AGPRs on targets which do not have them | Stanislav Mekhanoshin | 2019-07-30 | 1 | -11/+9 |
| | | | | | | | Differential Revision: https://reviews.llvm.org/D65471 llvm-svn: 367347 | ||||
| * | [AMDGPU] use v32f32 for 3 mfma intrinsics | Stanislav Mekhanoshin | 2019-07-12 | 1 | -3/+7 |
| | | | | | | | | | | These should really use v32f32, but were defined as v32i32 due to the lack of the v32f32 type. Differential Revision: https://reviews.llvm.org/D64667 llvm-svn: 365972 | ||||
| * | [AMDGPU] gfx908 agpr spilling | Stanislav Mekhanoshin | 2019-07-11 | 1 | -0/+288 |
| Differential Revision: https://reviews.llvm.org/D64594 llvm-svn: 365833 | |||||
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index : bcm5719-llvm | |
| Project Ortega BCM5719 LLVM | Raptor Computing Systems |
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