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* [AMDGPU] Switch scalarize global loads ON by defaultAlexander Timofeev2017-07-041-2/+2
| | | | | | Differential revision: https://reviews.llvm.org/D34407 llvm-svn: 307097
* Revert r307026, "[AMDGPU] Switch scalarize global loads ON by default"NAKAMURA Takumi2017-07-041-2/+2
| | | | | | | | | It broke a testcase. Failing Tests (1): LLVM :: CodeGen/AMDGPU/alignbit-pat.ll llvm-svn: 307054
* [AMDGPU] Switch scalarize global loads ON by defaultAlexander Timofeev2017-07-031-2/+2
| | | | | | Differential revision: https://reviews.llvm.org/D34407 llvm-svn: 307026
* Allow to truncate left shift with non-constant shift amountStanislav Mekhanoshin2017-06-281-0/+74
| | | | | | | | | | | That is pretty common for clang to produce code like (shl %x, (and %amt, 31)). In this situation we can still perform trunc (shl) into shl (trunc) conversion given the known value range of shift amount. Differential Revision: https://reviews.llvm.org/D34723 llvm-svn: 306499
* AMDGPU: Mark all unspecified CC functions in tests as amdgpu_kernelMatt Arsenault2017-03-211-20/+20
| | | | | | | | | | | | Currently the default C calling convention functions are treated the same as compute kernels. Make this explicit so the default calling convention can be changed to a non-kernel. Converted with perl -pi -e 's/define void/define amdgpu_kernel void/' on the relevant test directories (and undoing in one place that actually wanted a non-kernel). llvm-svn: 298444
* AMDGPU/SI: Enable load-store-opt by default.Changpeng Fang2016-05-261-4/+4
| | | | | | | | | | Summary: Enable load-store-opt by default, and update LIT tests. Reviewers: arsenm Differential Revision: http://reviews.llvm.org/D20694 llvm-svn: 270894
* AMDGPU/SI: Enable the post-ra schedulerTom Stellard2016-04-301-9/+9
| | | | | | | | | | | | | | Summary: This includes a hazard recognizer implementation to replace some of the hazard handling we had during frame index elimination. Reviewers: arsenm Subscribers: qcolombet, arsenm, llvm-commits Differential Revision: http://reviews.llvm.org/D18602 llvm-svn: 268143
* DAGCombiner: Reduce truncated shl widthMatt Arsenault2016-04-291-0/+123
| | | | llvm-svn: 268094
* AMDGPU: Reduce 64-bit SRAsMatt Arsenault2016-01-181-3/+11
| | | | llvm-svn: 258096
* AMDGPU: Split 64-bit and of constant upMatt Arsenault2016-01-181-6/+9
| | | | | | | | | | This breaks the tests that were meant for testing 64-bit inline immediates, so move those to shl where they won't be broken up. This should be repeated for the other related bit ops. llvm-svn: 258095
* AMDGPU: Generalize shl combineMatt Arsenault2016-01-181-0/+47
| | | | | | | Reduce 64-bit shl with constant > 32. We already special cased this for the == 32 case, but this also works for any >= 32 constant. llvm-svn: 258092
* AMDGPU: Reduce 64-bit lshr by constant to 32-bitMatt Arsenault2016-01-181-0/+64
64-bit shifts are very slow on some subtargets. llvm-svn: 258090
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