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| author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2016-01-18 22:09:04 +0000 |
|---|---|---|
| committer | Matt Arsenault <Matthew.Arsenault@amd.com> | 2016-01-18 22:09:04 +0000 |
| commit | 33e3ecee0c44169f11d1fc4472250c1346e68a4e (patch) | |
| tree | aefe8d1832cb203a53914cc47e3ecd8bb4bf5432 /llvm/test/CodeGen/AMDGPU/shift-i64-opts.ll | |
| parent | 6e3a45193aa927de0d4a677594f74c31cfc26727 (diff) | |
| download | bcm5719-llvm-33e3ecee0c44169f11d1fc4472250c1346e68a4e.tar.gz bcm5719-llvm-33e3ecee0c44169f11d1fc4472250c1346e68a4e.zip | |
AMDGPU: Reduce 64-bit SRAs
llvm-svn: 258096
Diffstat (limited to 'llvm/test/CodeGen/AMDGPU/shift-i64-opts.ll')
| -rw-r--r-- | llvm/test/CodeGen/AMDGPU/shift-i64-opts.ll | 14 |
1 files changed, 11 insertions, 3 deletions
diff --git a/llvm/test/CodeGen/AMDGPU/shift-i64-opts.ll b/llvm/test/CodeGen/AMDGPU/shift-i64-opts.ll index 2fab00377d9..b47e68a01fa 100644 --- a/llvm/test/CodeGen/AMDGPU/shift-i64-opts.ll +++ b/llvm/test/CodeGen/AMDGPU/shift-i64-opts.ll @@ -105,10 +105,18 @@ define void @shl_i64_const_63(i64 addrspace(1)* %out, i64 addrspace(1)* %in) { ; ashr (i64 x), 63 => (ashr lo(x), 31), lo(x) -; GCN-LABEL: {{^}}ashr_i64_const_gt_32: -define void @ashr_i64_const_gt_32(i64 addrspace(1)* %out, i64 addrspace(1)* %in) { +; GCN-LABEL: {{^}}ashr_i64_const_32: +define void @ashr_i64_const_32(i64 addrspace(1)* %out, i64 addrspace(1)* %in) { %val = load i64, i64 addrspace(1)* %in - %shl = ashr i64 %val, 35 + %shl = ashr i64 %val, 32 + store i64 %shl, i64 addrspace(1)* %out + ret void +} + +; GCN-LABEL: {{^}}ashr_i64_const_63: +define void @ashr_i64_const_63(i64 addrspace(1)* %out, i64 addrspace(1)* %in) { + %val = load i64, i64 addrspace(1)* %in + %shl = ashr i64 %val, 63 store i64 %shl, i64 addrspace(1)* %out ret void } |
