summaryrefslogtreecommitdiffstats
path: root/llvm/test/CodeGen/AMDGPU/scratch-buffer.ll
Commit message (Collapse)AuthorAgeFilesLines
* AMDGPU/SI: Avoid creating unnecessary copies in the SIFixSGPRCopies passTom Stellard2016-11-161-1/+3
| | | | | | | | | | | | | | | | | | | | | | Summary: 1. Don't try to copy values to and from the same register class. 2. Replace copies with of registers with immediate values with v_mov/s_mov instructions. The main purpose of this change is to make MachineSink do a better job of determining when it is beneficial to split a critical edge, since the pass assumes that copies will become move instructions. This prevents a regression in uniform-cfg.ll if we enable critical edge splitting for AMDGPU. Reviewers: arsenm Subscribers: arsenm, kzhuravl, llvm-commits Differential Revision: https://reviews.llvm.org/D23408 llvm-svn: 287131
* Reapply "AMDGPU: Don't use offen if it is 0"Matt Arsenault2016-10-261-4/+3
| | | | | | This reverts r283003 llvm-svn: 285203
* Revert "AMDGPU: Don't use offen if it is 0"Mehdi Amini2016-10-011-3/+4
| | | | | | | This reverts commit r282999. Tests are not passing: http://lab.llvm.org:8011/builders/clang-x86_64-linux-selfhost-modules/builds/20038 llvm-svn: 283003
* AMDGPU: Don't use offen if it is 0Matt Arsenault2016-10-011-4/+3
| | | | | | This removes many re-initializations of a base register to 0. llvm-svn: 282999
* AMDGPU: Run LoadStoreVectorizer pass by defaultMatt Arsenault2016-09-091-2/+2
| | | | llvm-svn: 281112
* AMDGPU: Remove SignBitIsZero for mubuf scratch offsetsMatt Arsenault2016-03-211-8/+5
| | | | | | | These instructions do not have the same negative base address problem that DS instructions do on SI. llvm-svn: 263964
* AMDGPU: More bits of frame index are known to be zeroMatt Arsenault2016-02-271-6/+3
| | | | | | | | | | | | The maximum private allocation for the whole GPU is 4G, so the maximum possible index for a single workitem is the maximum size divided by the smallest granularity for a dispatch. This increases the number of known zero high bits, which enables more offset folding. The maximum private size per workitem with this is 128M but may be smaller still. llvm-svn: 262153
* AMDGPU: Add sdst operand to VOP2b instructionsMatt Arsenault2015-08-291-1/+1
| | | | | | | | | | The VOP3 encoding of these allows any SGPR pair for the i1 output, but this was forced before to always use vcc. This doesn't yet try to use this, but does add the operand to the definitions so the main change is adding vcc to the output of the VOP2 encoding. llvm-svn: 246358
* AMDPGU/SI: Negative offsets aren't allowed in MUBUF's vaddr operandTom Stellard2015-07-161-11/+40
| | | | | | | | | | Reviewers: arsenm Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D11226 llvm-svn: 242434
* R600 -> AMDGPU renameTom Stellard2015-06-131-0/+87
llvm-svn: 239657
OpenPOWER on IntegriCloud