| Commit message (Collapse) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | AMDGPU: Fix i16 arithmetic pattern redundancy | Matt Arsenault | 2019-10-08 | 1 | -20/+134 |
| | | | | | | | | | | | | | | | There were 2 problems here. First, these patterns were duplicated to handle the inverted shift operands instead of using the commuted PatFrags. Second, the point of the zext folding patterns don't apply to the non-0ing high subtargets. They should be skipped instead of inserting the extension. The zeroing high code would be emitted when necessary anyway. This was also emitting unnecessary zexts in cases where the high bits were undefined. llvm-svn: 374092 | ||||
| * | [AMDGPU] gfx1010 VOP3 and VOP3P implementation | Stanislav Mekhanoshin | 2019-04-26 | 1 | -0/+96 |
| Differential Revision: https://reviews.llvm.org/D61202 llvm-svn: 359328 | |||||
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index : bcm5719-llvm | |
| Project Ortega BCM5719 LLVM | Raptor Computing Systems |
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