| Commit message (Collapse) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | AMDGPU: Handle partial shift reduction for variable shifts | Matt Arsenault | 2018-05-09 | 1 | -0/+36 |
| | | | | | | | | If the variable shift amount has known bits, we can still reduce the shift. llvm-svn: 331917 | ||||
| * | AMDGPU: Partially shrink 64-bit shifts if reduced to 16-bit | Matt Arsenault | 2018-05-09 | 1 | -0/+102 |
| This is an extension of an existing combine to reduce wider shls if the result fits in the final result type. This introduces the same combine, but reduces the shift to a middle sized type to avoid the slow 64-bit shift. llvm-svn: 331916 | |||||
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index : bcm5719-llvm | |
| Project Ortega BCM5719 LLVM | Raptor Computing Systems |
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