| Commit message (Collapse) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | [AMDGPU] Promote uniform i16 ops to i32 ops for targets that have 16 bit ↵ | Konstantin Zhuravlyov | 2016-09-28 | 1 | -197/+0 |
| | | | | | | | | | instructions Differential Revision: https://reviews.llvm.org/D24125 llvm-svn: 282624 | ||||
| * | AMDGPU: Select mulhi 24-bit instructions | Matt Arsenault | 2016-08-27 | 1 | -23/+151 |
| | | | | | llvm-svn: 279902 | ||||
| * | AMDGPU: Run r600 tests last | Matt Arsenault | 2016-05-05 | 1 | -2/+2 |
| | | | | | llvm-svn: 268672 | ||||
| * | AMDGPU: Avoid using 64-bit shift for i64 (shl x, 32) | Matt Arsenault | 2015-07-14 | 1 | -9/+11 |
| | | | | | | | | | | | | | | | | | | This can be done only with moves which theoretically will optimize better later. Although this transform increases the instruction count, it should be code size / cycle count neutral in the worst VALU case. It also seems to slightly improve a couple of testcases due to other DAG combines this exposes. This is probably slightly worse for the SALU case, so it might be better to handle this during moveToVALU, although then you lose some simplifications like the load width reducing in the simple testcase. llvm-svn: 242177 | ||||
| * | R600 -> AMDGPU rename | Tom Stellard | 2015-06-13 | 1 | -0/+67 |
| llvm-svn: 239657 | |||||
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index : bcm5719-llvm | |
| Project Ortega BCM5719 LLVM | Raptor Computing Systems |
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