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Differential Revision: https://reviews.llvm.org/D61535
llvm-svn: 360087
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Differential Revision: https://reviews.llvm.org/D59517
llvm-svn: 356946
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Differential Revision: https://reviews.llvm.org/D55093
llvm-svn: 348014
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Add a pass to fixup various vector ISel issues.
Currently we handle converting GLOBAL_{LOAD|STORE}_*
and GLOBAL_Atomic_* instructions into their _SADDR variants.
This involves feeding the sreg into the saddr field of the new instruction.
llvm-svn: 347008
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- Make code easier to maintain.
- Avoid generating waitcnts for VMEM if the address sppace does not involve VMEM.
- Add support to generate waitcnts for LDS and GDS memory.
Differential Revision: https://reviews.llvm.org/D47504
llvm-svn: 334241
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llvm-svn: 325042
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Those should have glc bit set for system and agent synchronization scopes
llvm-svn: 324314
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This requires corresponding clang change.
Differential Revision: https://reviews.llvm.org/D40955
llvm-svn: 324101
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llvm-svn: 316590
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- memory-legalizer-atomic-load.ll -> memory-legalizer-load.ll
- memory-legalizer-atomic-store.ll -> memory-legalizer-store.ll
llvm-svn: 316586
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