Commit message (Collapse) | Author | Age | Files | Lines | |
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* | AMDGPU: Remove legacy rsq.clamped intrinsic | Matt Arsenault | 2016-07-15 | 1 | -25/+0 |
| | | | | | | | | Mesa still has a use of llvm.AMDGPU.rsq.f64 remaining. Also fix mismatch with non-IEEE rsq selecting to IEEE rsq. llvm-svn: 275617 | ||||
* | AMDGPU/SI: Enable the post-ra scheduler | Tom Stellard | 2016-04-30 | 1 | -3/+3 |
| | | | | | | | | | | | | | | Summary: This includes a hazard recognizer implementation to replace some of the hazard handling we had during frame index elimination. Reviewers: arsenm Subscribers: qcolombet, arsenm, llvm-commits Differential Revision: http://reviews.llvm.org/D18602 llvm-svn: 268143 | ||||
* | AMDGPU: Rename intrinsics to use amdgcn prefix | Matt Arsenault | 2016-01-22 | 1 | -0/+2 |
| | | | | | | | | | | | The intrinsic target prefix should match the target name as it appears in the triple. This is not yet complete, but gets most of the important ones. llvm.AMDGPU.* intrinsics used by mesa and libclc are still handled for compatability for now. llvm-svn: 258557 | ||||
* | R600 -> AMDGPU rename | Tom Stellard | 2015-06-13 | 1 | -0/+23 |
llvm-svn: 239657 |