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path: root/llvm/test/CodeGen/AMDGPU/inserted-wait-states.mir
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* AMDGPU: Fix tests using old number for constant address spaceMatt Arsenault2018-09-101-1/+1
* [DebugInfo] Add DILabel metadata and intrinsic llvm.dbg.label.Shiva Chen2018-05-091-1/+1
* [AMDGPU] added writelane intrinsicTim Renouf2018-02-281-2/+2
* [AMDGPU] Switch to the new addr space mapping by defaultYaxun Liu2018-02-021-3/+3
* Followup on Proposal to move MIR physical register namespace to '$' sigil.Puyan Lotfi2018-01-311-99/+99
* [CodeGen] Always use `printReg` to print registers in both MIR and debugFrancis Visoiu Mistrih2017-11-301-1/+1
* AMDGPU: Move hazard avoidance out of waitcnt pass.Matt Arsenault2017-11-171-4/+4
* [AMDGPU] Add pseudo "old" source to all DPP instructionsConnor Abbott2017-08-071-2/+2
* [AMDGPU] Add missing hazard for DPP-after-EXEC-writeConnor Abbott2017-08-041-0/+35
* AMDGPU: Start adding offset fields to flat instructionsMatt Arsenault2017-06-121-5/+5
* AMDGPU: Remove tfe bit from flat instruction definitionsMatt Arsenault2017-05-111-5/+5
* MIParser/MIRPrinter: Compute block successors if not explicitely specifiedMatthias Braun2017-05-051-20/+0
* AMDGPU: Mark all unspecified CC functions in tests as amdgpu_kernelMatt Arsenault2017-03-211-11/+11
* AMDGPU: Merge initial gfx9 supportMatt Arsenault2017-02-181-0/+214
* AMDGPU: Remove modifiers from v_div_scale_*Matt Arsenault2017-01-191-1/+1
* Move .mir tests to appropriate directoriesMatthias Braun2016-12-091-0/+333
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