Commit message (Collapse) | Author | Age | Files | Lines | |
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* | [AMDGPU] gfx1010 core wave32 changes | Stanislav Mekhanoshin | 2019-06-20 | 1 | -5/+22 |
| | | | | | | Differential Revision: https://reviews.llvm.org/D63204 llvm-svn: 363934 | ||||
* | AMDGPU: Correct maximum possible private allocation size | Matt Arsenault | 2019-05-23 | 1 | -10/+21 |
| | | | | | | | | | | | | | | | | We were assuming a much larger possible per-wave visible stack allocation than is possible: https://github.com/RadeonOpenCompute/ROCR-Runtime/blob/faa3ae51388517353afcdaf9c16621f879ef0a59/src/core/runtime/amd_gpu_agent.cpp#L70 Based on this, we can assume the high 15 bits of a frame index or sret are 0. The frame index value is the per-lane offset, so the maximum frame index value is MAX_WAVE_SCRATCH / wavesize. Remove the corresponding subtarget feature and option that made this configurable. llvm-svn: 361541 | ||||
* | [AMDGPU] Switch to the new addr space mapping by default | Yaxun Liu | 2018-02-02 | 1 | -6/+6 |
| | | | | | | | | This requires corresponding clang change. Differential Revision: https://reviews.llvm.org/D40955 llvm-svn: 324101 | ||||
* | AMDGPU: Don't use MUBUF vaddr if address may overflow | Matt Arsenault | 2017-11-15 | 1 | -0/+31 |
Effectively revert r263964. Before we would not allow this if vaddr was not known to be positive. llvm-svn: 318240 |