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* AMDGPU: Switch backend default max workgroup size to 1024Matt Arsenault2019-11-131-1/+25
| | | | | | | | | | | | | Previously this would default to 256, not the maximum supported size of 1024. Using a maximum lower than the hardware maximum requires language runtimes to enforce this limit for correctness, which no language has correctly done. Switch the default to the conservatively correct maximum, and force frontends to opt-in to the more optimal 256 default maximum. I don't really understand why the changes in occupancy-levels.ll increased the computed occupancy, which I expected to decrease. I'm not sure if these tests should be forcing the old maximum.
* [llvm-readobj] Change -long-option to --long-option in tests. NFCFangrui Song2019-05-011-3/+3
| | | | | | | | | | We use both -long-option and --long-option in tests. Switch to --long-option for consistency. In the "llvm-readelf" mode, -long-option is discouraged as it conflicts with grouped short options and it is not accepted by GNU readelf. While updating the tests, change llvm-readobj -s to llvm-readobj -S to reduce confusion ("s" is --section-headers in llvm-readobj but --symbols in llvm-readelf). llvm-svn: 359649
* AMDGPU: Enable code object v3 for AMDHSA onlyKonstantin Zhuravlyov2018-11-151-3/+3
| | | | | | Differential Revision: https://reviews.llvm.org/D54186 llvm-svn: 346923
* Revert r345542: AMDGPU: Enable code object v3 by defaultKonstantin Zhuravlyov2018-10-301-3/+3
| | | | | | It breaks mesa. llvm-svn: 345662
* AMDGPU: Enable code object v3 by defaultKonstantin Zhuravlyov2018-10-291-3/+3
| | | | | | Differential Revision: https://reviews.llvm.org/D53525 llvm-svn: 345542
* AMDGPU: Add pass to lower kernel arguments to loadsMatt Arsenault2018-06-261-13/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This replaces most argument uses with loads, but for now not all. The code in SelectionDAG for calling convention lowering is actively harmful for amdgpu_kernel. It attempts to split the argument types into register legal types, which results in low quality code for arbitary types. Since all kernel arguments are passed in memory, we just want the raw types. I've tried a couple of methods of mitigating this in SelectionDAG, but it's easier to just bypass this problem alltogether. It's possible to hack around the problem in the initial lowering, but the real problem is the DAG then expects to be able to use CopyToReg/CopyFromReg for uses of the arguments outside the block. Exposing the argument loads in the IR also has the advantage that the LoadStoreVectorizer can merge them. I'm not sure the best approach to dealing with the IR argument list is. The patch as-is just leaves the IR arguments in place, so all the existing code will still compute the same kernarg size and pointlessly lowers the arguments. Arguably the frontend should emit kernels with an empty argument list in the first place. Alternatively a dummy array could be inserted as a single argument just to reserve space. This does have some disadvantages. Local pointer kernel arguments can no longer have AssertZext placed on them as the equivalent !range metadata is not valid on pointer typed loads. This is mostly bad for SI which needs to know about the known bits in order to use the DS instruction offset, so in this case this is not done. More importantly, this skips noalias arguments since this pass does not yet convert this to the equivalent !alias.scope and !noalias metadata. Producing this metadata correctly seems to be tricky, although this logically is the same as inlining into a function which doesn't exist. Additionally, exposing these loads to the vectorizer may result in degraded aliasing information if a pointer load is merged with another argument load. I'm also not entirely sure this is preserving the current clover ABI, although I would greatly prefer if it would stop widening arguments and match the HSA ABI. As-is I think it is extending < 4-byte arguments to 4-bytes but doesn't align them to 4-bytes. llvm-svn: 335650
* [AMDGPU] Add perf hints to functionsStanislav Mekhanoshin2018-05-251-6/+4
| | | | | | | | | | | | | | | This is adoption of HSAIL perfhint pass. Two types of hints are produced: 1. Function is memory bound. 2. Kernel can use wave limiter. Currently these hints are used in the scheduler. If a function is suspected to be memory bound we allow occupancy to decrease to 4 waves in the course of scheduling. Differential Revision: https://reviews.llvm.org/D46992 llvm-svn: 333289
* AMDGPU: Add num spilled s/vgprs to metadataKonstantin Zhuravlyov2017-11-281-17/+125
| | | | | | | | This was requested by tools. Differential Revision: https://reviews.llvm.org/D40321 llvm-svn: 319192
* AMDGPU: Rename MaxFlatWorkgroupSize to MaxFlatWorkGroupSize for consistencyKonstantin Zhuravlyov2017-10-181-1/+1
| | | | | | Differential Revision: https://reviews.llvm.org/D38957 llvm-svn: 316097
* AMDGPU: Start generating metadata for MaxFlatWorkGroupSizeKonstantin Zhuravlyov2017-10-171-10/+11
| | | | | | Differential Revision: https://reviews.llvm.org/D38958 llvm-svn: 316024
* AMDGPU: Bring HSA metadata on par with the specificationKonstantin Zhuravlyov2017-10-141-11/+12
| | | | | | Differential Revision: https://reviews.llvm.org/D38753 llvm-svn: 315821
* llvm-readobj: Print AMDGPU note contentsKonstantin Zhuravlyov2017-10-141-3/+3
| | | | | | Differential Revision: https://reviews.llvm.org/D38752 llvm-svn: 315819
* AMDGPU/NFC: Rename code object metadata as HSA metadataKonstantin Zhuravlyov2017-10-111-0/+32
- Rename AMDGPUCodeObjectMetadata to AMDGPUMetadata (PAL metadata will be included in this file in the follow up change) - Rename AMDGPUCodeObjectMetadataStreamer to AMDGPUHSAMetadataStreamer - Introduce HSAMD namespace - Other minor name changes in function and test names llvm-svn: 315522
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