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* AMDGPU: Remove dx10-clamp from subtarget featuresMatt Arsenault2019-03-291-1/+23
| | | | | | | | | | | | | | | | | | Since this can be set with s_setreg*, it should not be a subtarget property. Set a default based on the calling convention, and Introduce a new amdgpu-dx10-clamp attribute to override this if desired. Also introduce a new amdgpu-ieee attribute to match. The values need to match to allow inlining. I think it is OK for the caller's dx10-clamp attribute to override the callee, but there doesn't appear to be the infrastructure to do this currently without definining the attribute in the generic Attributes.td. Eventually the calling convention lowering will need to insert a mode switch somewhere for these. llvm-svn: 357302
* AMDGPU: Enable code object v3 for AMDHSA onlyKonstantin Zhuravlyov2018-11-151-7/+7
| | | | | | Differential Revision: https://reviews.llvm.org/D54186 llvm-svn: 346923
* Revert r345542: AMDGPU: Enable code object v3 by defaultKonstantin Zhuravlyov2018-10-301-7/+7
| | | | | | It breaks mesa. llvm-svn: 345662
* AMDGPU: Enable code object v3 by defaultKonstantin Zhuravlyov2018-10-291-7/+7
| | | | | | Differential Revision: https://reviews.llvm.org/D53525 llvm-svn: 345542
* AMDGPU: Mark all unspecified CC functions in tests as amdgpu_kernelMatt Arsenault2017-03-211-7/+7
| | | | | | | | | | | | Currently the default C calling convention functions are treated the same as compute kernels. Make this explicit so the default calling convention can be changed to a non-kernel. Converted with perl -pi -e 's/define void/define amdgpu_kernel void/' on the relevant test directories (and undoing in one place that actually wanted a non-kernel). llvm-svn: 298444
* AMDGPU: Redefine clamp node as clamp 0.0-1.0Matt Arsenault2017-02-211-0/+11
| | | | | | | | | | | Change implementation to use max instead of add. min/max/med3 do not flush denormals regardless of the mode, so it is OK to use it whether or not they are enabled. Also allow using clamp with f16, and use knowledge of dx10_clamp. llvm-svn: 295788
* AMDGPU: Combine fp16/fp64 subtarget featuresMatt Arsenault2017-01-231-4/+4
| | | | | | | The same control register controls both, and are set to the same defaults. Keep the old names around as aliases. llvm-svn: 292837
* AMDGPU : Add a function to enable and disable IEEEBit for SC and shaderWei Ding2016-10-191-6/+6
| | | | | | | | respectively. Differential Revision: http://reviews.llvm.org/D25789 llvm-svn: 284655
* [AMDGPU] Assembler: rename amd_kernel_code_t asm names according to specSam Kolton2016-09-091-18/+18
| | | | | | | | | | | | | | Summary: Also removed duplicate code from AMDGPUTargetAsmStreamer. This change only change how amd_kernel_code_t is parsed and printed. No variable names are changed. Reviewers: vpykhtin, tstellarAMD Subscribers: arsenm, wdng, nhaehnle Differential Revision: https://reviews.llvm.org/D24296 llvm-svn: 281028
* AMDGPU: Simplify tests with per function subtargetsMatt Arsenault2016-07-091-5/+63
| | | | llvm-svn: 274971
* AMDGPU: Set DX10Clamp bitMatt Arsenault2016-01-281-0/+10
llvm-svn: 259088
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