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* AMDGPU: Remove remnants of old address space mappingMatt Arsenault2018-08-311-1/+1
| | | | llvm-svn: 341165
* [AMDGPU] fix test to survive more FP undef constant foldingSanjay Patel2018-03-081-5/+6
| | | | llvm-svn: 327066
* [AMDGPU] fix test to survive the most basic undef constant foldingSanjay Patel2018-03-081-1/+1
| | | | | | | This will likely need to be changed again for anything more than: fmul undef, undef -> undef llvm-svn: 327034
* Recommit CodeGen: Fix assertion in machine inst sheduler due to llvm.dbg.valueYaxun Liu2017-12-151-0/+106
| | | | | | The regression on ppc64 was not due to this commit. llvm-svn: 320788
* Revert CodeGen: Fix assertion in machine inst sheduler due to llvm.dbg.valueYaxun Liu2017-12-141-106/+0
| | | | | | This commit might have caused regression on ppc64. Revert it to verify that. llvm-svn: 320712
* CodeGen: Fix assertion in machine inst sheduler due to llvm.dbg.valueYaxun Liu2017-12-131-0/+106
Two issues were found about machine inst scheduler when compiling ProRender with -g for amdgcn target: GCNScheduleDAGMILive::schedule tries to update LiveIntervals for DBG_VALUE, which it should not since DBG_VALUE is not mapped in LiveIntervals. when DBG_VALUE is the last instruction of MBB, ScheduleDAGInstrs::buildSchedGraph and ScheduleDAGMILive::scheduleMI does not move RPTracker properly, which causes assertion. This patch fixes that. Differential Revision: https://reviews.llvm.org/D41132 llvm-svn: 320650
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