Commit message (Collapse) | Author | Age | Files | Lines | |
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* | [AMDGPU] gfx1010 VMEM and SMEM implementation | Stanislav Mekhanoshin | 2019-04-30 | 1 | -4/+4 |
| | | | | | | Differential Revision: https://reviews.llvm.org/D61330 llvm-svn: 359621 | ||||
* | [AMDGPU] Add support for immediate operand for S_ENDPGM | David Stuttard | 2019-03-12 | 1 | -1/+1 |
| | | | | | | | | | | | | | | | | | Summary: Add support for immediate operand in S_ENDPGM Change-Id: I0c56a076a10980f719fb2a8f16407e9c301013f6 Reviewers: alexshap Subscribers: qcolombet, arsenm, kzhuravl, jvesely, wdng, nhaehnle, yaxunl, tpr, t-tye, eraman, arphaman, Petar.Avramovic, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D59213 llvm-svn: 355902 | ||||
* | Followup on Proposal to move MIR physical register namespace to '$' sigil. | Puyan Lotfi | 2018-01-31 | 1 | -13/+13 |
| | | | | | | | | | | | | Discussed here: http://lists.llvm.org/pipermail/llvm-dev/2018-January/120320.html In preparation for adding support for named vregs we are changing the sigil for physical registers in MIR to '$' from '%'. This will prevent name clashes of named physical register with named vregs. llvm-svn: 323922 | ||||
* | [AMDGPU] Prevent post-RA scheduler from breaking memory clauses | Stanislav Mekhanoshin | 2017-09-19 | 1 | -0/+31 |
The pre-RA scheduler does load/store clustering, but post-RA scheduler undoes it. Add mutation to prevent it. Differential Revision: https://reviews.llvm.org/D38014 llvm-svn: 313670 |