| Commit message (Collapse) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | AMDGPU: Introduce a flag to disable mul24 intrinsic formation | Matt Arsenault | 2019-08-24 | 1 | -54/+165 |
| | | | | | llvm-svn: 369856 | ||||
| * | AMDGPU: Add 24-bit mul intrinsics | Matt Arsenault | 2019-07-15 | 1 | -0/+494 |
| Insert these during codegenprepare. This works around a DAG issue where generic combines eliminate the and asserting the high bits are zero, which then exposes an unknown read source to the mul combine. It doesn't worth the hassle of trying to insert an AssertZext or something to try to deal with it. llvm-svn: 366094 | |||||
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index : bcm5719-llvm | |
| Project Ortega BCM5719 LLVM | Raptor Computing Systems |
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