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* AMDGPU/GlobalISel: Allow scalar s1 and/or/xorMatt Arsenault2019-07-151-144/+1
| | | | | | | | If a 1-bit value is in a 32-bit VGPR, the scalar opcodes set SCC to whether the result is 0. If the inputs are SCC, these can be copied to a 32-bit SGPR to produce an SCC result. llvm-svn: 366125
* AMDGPU/GlobalISel: Add tests for regbankselect of v2s16 and/or/xorMatt Arsenault2019-06-241-0/+65
| | | | llvm-svn: 364244
* AMDGPU/GlobalISel: Correct regbank for 1-bit and/or/xorMatt Arsenault2019-05-161-14/+14
| | | | | | Bool values should use the scc/vcc regbank since r350611. llvm-svn: 360877
* RegBankSelect: Handle slightly more complex value mappingsMatt Arsenault2019-02-251-32/+108
| | | | | | | | Try to use concat_vectors. Also remove unnecessary assert on pointers. Fixes asserting for <4 x s16> operations and 64-bit pointers for AMDGPU. llvm-svn: 354828
* GlobalISel: Enforce operand types for constantsMatt Arsenault2019-02-041-6/+6
| | | | | | | | A number of of tests were using imm operands, not cimm. Since CSE relies on the exact ConstantInt* pointer used, and implicit conversions are generally evil, also enforce the bitsize of the types. llvm-svn: 353113
* RegBankSelect: Support some more complex part mappingsMatt Arsenault2019-01-241-0/+386
| | | | llvm-svn: 352123
* AMDGPU/GlobalISel: Introduce vcc reg bankMatt Arsenault2019-01-081-7/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | I'm not entirely sure this is the correct thing to do with the global isel philosophy, but I think this is necessary to handle how differently SGPRs are used normally vs. from a condition. For example, it makes sense to allow a copy from a VGPR to an SGPR, but it makes no sense to allow a copy from VGPRs to SGPRs used as select mask. This avoids regbankselecting strange code with a truncate feeding directly into a condition field. Now a copy is forced from sgpr(s1) to vcc, which is more sensible to handle. Some of these issues could probably avoided with making enough operations resulting in i1 illegal. I think we can't avoid this register bank for legality. For example, an i1 and where one source is from a truncate, and one source is a compare needs some kind of copy inserted to make sure both are in condition registers. llvm-svn: 350611
* AMDGPU: Make i1/i64/v2i32 and/or/xor legalMatt Arsenault2018-12-201-8/+148
| | | | | | | The 64-bit types do depend on the register bank, but that's another issue to deal with later. llvm-svn: 349716
* [globalisel] Remove redundant -global-isel option from tests that use ↵Daniel Sanders2018-05-051-2/+2
| | | | | | | | | | | -run-pass. NFC As Roman Tereshin pointed out in https://reviews.llvm.org/D45541, the -global-isel option is redundant when -run-pass is given. -global-isel sets up the GlobalISel passes in the pass manager but -run-pass skips that entirely and configures it's own pipeline. llvm-svn: 331603
* AMDGPU/GlobalISel: Define instruction mapping for G_ANDMatt Arsenault2018-03-021-0/+68
Patch by Tom Stellard llvm-svn: 326523
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