| Commit message (Collapse) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | AMDGPU: Relax 32-bit SGPR register class | Matt Arsenault | 2019-10-18 | 1 | -2/+2 |
| | | | | | | | | | | | | Mostly use SReg_32 instead of SReg_32_XM0 for arbitrary values. This will allow the register coalescer to do a better job eliminating copies to m0. For GlobalISel, as a terrible hack, use SGPR_32 for things that should use SCC until booleans are solved. llvm-svn: 375267 | ||||
| * | AMDGPU/GlobalISel: Allow selection of scalar min/max | Matt Arsenault | 2019-09-21 | 1 | -10/+5 |
| | | | | | | | | | | I believe all of the uniform/divergent pattern predicates are redundant and can be removed. The uniformity bit already influences the register class, and nothhing has broken when I've removed this and others. llvm-svn: 372450 | ||||
| * | GlobalISel: Add GINodeEquiv for min/max | Matt Arsenault | 2019-07-01 | 1 | -0/+83 |
| llvm-svn: 364759 | |||||
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index : bcm5719-llvm | |
| Project Ortega BCM5719 LLVM | Raptor Computing Systems |
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