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* AMDGPU/GlobalISel: Don't use XEXEC class for SGPRsMatt Arsenault2020-01-121-2/+2
| | | | | We don't use the xexec register classes for arbitrary values anymore. Avoids a test variance beween GlobalISel and SelectionDAG>
* AMDGPU: Relax 32-bit SGPR register classMatt Arsenault2019-10-181-10/+10
| | | | | | | | | | | Mostly use SReg_32 instead of SReg_32_XM0 for arbitrary values. This will allow the register coalescer to do a better job eliminating copies to m0. For GlobalISel, as a terrible hack, use SGPR_32 for things that should use SCC until booleans are solved. llvm-svn: 375267
* AMDGPU/GlobalISel: Fix some broken run linesMatt Arsenault2019-09-161-2/+2
| | | | llvm-svn: 371992
* AMDGPU/GlobalISel: Fix VALU s16 fnegMatt Arsenault2019-09-161-11/+9
| | | | llvm-svn: 371948
* GlobalISel/TableGen: Handle REG_SEQUENCE patternsMatt Arsenault2019-09-101-10/+21
| | | | | | | | The scalar f64 patterns don't work yet because they fail on multiple results from the unused implicit def of scc in the result bit operation. llvm-svn: 371542
* AMDGPU/GlobalISel: Select G_FABS/G_FNEGMatt Arsenault2019-09-101-0/+513
f64 doesn't work yet because tablegen currently doesn't handlde REG_SEQUENCE. This does regress some multi use VALU fneg cases since now the immediate remains in an SGPR, and more moves are used for legalizing the xor. This is a SIFixSGPRCopies deficiency. llvm-svn: 371540
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