| Commit message (Collapse) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | AMDGPU/GlobalISel: Fix import of zext of s16 op patterns | Matt Arsenault | 2020-01-09 | 1 | -4/+2 |
| | | |||||
| * | AMDGPU: Relax 32-bit SGPR register class | Matt Arsenault | 2019-10-18 | 1 | -6/+6 |
| | | | | | | | | | | | | Mostly use SReg_32 instead of SReg_32_XM0 for arbitrary values. This will allow the register coalescer to do a better job eliminating copies to m0. For GlobalISel, as a terrible hack, use SGPR_32 for things that should use SCC until booleans are solved. llvm-svn: 375267 | ||||
| * | AMDGPU: Fix i16 arithmetic pattern redundancy | Matt Arsenault | 2019-10-08 | 1 | -12/+4 |
| | | | | | | | | | | | | | | | There were 2 problems here. First, these patterns were duplicated to handle the inverted shift operands instead of using the commuted PatFrags. Second, the point of the zext folding patterns don't apply to the non-0ing high subtargets. They should be skipped instead of inserting the extension. The zeroing high code would be emitted when necessary anyway. This was also emitting unnecessary zexts in cases where the high bits were undefined. llvm-svn: 374092 | ||||
| * | AMDGPU/GlobalISel: Fix selection of 16-bit shifts | Matt Arsenault | 2019-10-07 | 1 | -98/+270 |
| | | | | | llvm-svn: 373945 | ||||
| * | AMDGPU/GlobalISel: Select G_ASHR | Matt Arsenault | 2019-07-16 | 1 | -0/+203 |
| llvm-svn: 366257 | |||||
 |
index : bcm5719-llvm | |
| Project Ortega BCM5719 LLVM | Raptor Computing Systems |
| summaryrefslogtreecommitdiffstats |
|