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* GlobalISel: combine extracts & sequences created for legalizationTim Northover2016-08-302-10/+108
| | | | | | | | Legalization ends up creating many G_SEQUENCE/G_EXTRACT pairs which leads to inefficient codegen (even for -O0), so add a quick pass over the function to remove them again. llvm-svn: 280155
* GlobalISel: forbid physical registers on generic MIs.Tim Northover2016-08-307-62/+148
| | | | | | | | | | We're intending to move to a world where the type of a register is determined by its (unique) def. This is incompatible with physregs, which are untyped. It also means the other passes don't have to worry quite so much about register-class compatibility and inserting COPYs appropriately. llvm-svn: 280132
* GlobalISel: legalize frem to a libcall on AArch64.Tim Northover2016-08-291-0/+14
| | | | llvm-svn: 279988
* [GlobalISel] Add a fallback path to SDISel.Quentin Colombet2016-08-271-0/+19
| | | | | | | | | When global-isel fails on a MachineFunction MF, MF will be cleaned up and given to SDISel. Thanks to this fallback, we can already perform correctness test even if we support only a small portion of the functions in a test. llvm-svn: 279891
* Swift Calling Convetion: add support for AArch64.Manman Ren2016-08-261-0/+11
| | | | | | | | It will just be the same as the regular calling convention. rdar://28029509 llvm-svn: 279853
* AArch64: avoid assertion on illegal types in performFDivCombine.Tim Northover2016-08-261-0/+43
| | | | | | | | In the code to detect fixed-point conversions and make use of AArch64's special instructions, we weren't prepared for weird types. The fptosi direction got fixed recently, but not the similar sitofp code. llvm-svn: 279852
* [AArch64] Avoid materializing constant values when generating csel instructions.Chad Rosier2016-08-261-0/+99
| | | | | | Differential Revision: https://reviews.llvm.org/D23677 llvm-svn: 279849
* GlobalISel: mark G_FPEXT legal from float to double.Tim Northover2016-08-261-0/+6
| | | | llvm-svn: 279845
* GlobalISel: mark G_FCMP legal on float & double.Tim Northover2016-08-261-0/+35
| | | | llvm-svn: 279844
* GlobalISel: simplify G_ICMP legalization regime.Tim Northover2016-08-261-19/+2
| | | | | | | | | | | | | | It's unclear how the old %res(32) = G_ICMP { s32, s32 } intpred(eq), %0, %1 is actually different from an s1 verison %res(1) = G_ICMP { s1, s32 } intpred(eq), %0, %1 so we'll remove it for now. llvm-svn: 279843
* GlobalISel: legalize sdiv and srem operations.Tim Northover2016-08-261-0/+52
| | | | llvm-svn: 279842
* GlobalISel: legalize under-width divisions.Tim Northover2016-08-261-0/+42
| | | | llvm-svn: 279841
* GlobalISel: mark selects legalTim Northover2016-08-261-0/+16
| | | | llvm-svn: 279840
* GlobalISel: mark float/int conversions legalTim Northover2016-08-261-0/+66
| | | | llvm-svn: 279839
* [AArch64] Avoid materializing constant 1 by using csinc, rather than csel.Chad Rosier2016-08-262-6/+44
| | | | | | | | This is similar to what was done in r261675, but for CSINC rather than CSINV. Differential Revision: https://reviews.llvm.org/D23892 llvm-svn: 279822
* GlobalISel: mark simple ops legal even on types < 32-bit.Tim Northover2016-08-256-24/+6
| | | | | | | | The 32-bit variants of these operations don't depend on the bits not being operated on, so they also naturally model operations narrower than the actual register width. llvm-svn: 279760
* GlobalISel: mark pointer constants as legal on AArch64.Tim Northover2016-08-251-0/+3
| | | | llvm-svn: 279759
* GlobalISel: perform multi-step legalizationTim Northover2016-08-252-1/+8
| | | | llvm-svn: 279758
* GlobalISel: mark small extends as legal on AArch64Tim Northover2016-08-251-0/+73
| | | | llvm-svn: 279757
* MachineFunctionProperties/MIRParser: Rename AllVRegsAllocated->NoVRegs, ↵Matthias Braun2016-08-252-3/+0
| | | | | | | | | | | | | compute it Rename AllVRegsAllocated to NoVRegs. This avoids the connotation of running after register and simply describes that no vregs are used in a machine function. With that we can simply compute the property and do not need to dump/parse it in .mir files. Differential Revision: http://reviews.llvm.org/D23850 llvm-svn: 279698
* MIRParser/MIRPrinter: Compute HasInlineAsm instead of printing/parsing itMatthias Braun2016-08-242-3/+0
| | | | llvm-svn: 279680
* MachineRegisterInfo/MIR: Initialize tracksSubRegLiveness early, do not ↵Matthias Braun2016-08-242-3/+0
| | | | | | | | | | | | | print/parser it tracksSubRegLiveness only depends on the Subtarget and a cl::opt, there is not need to change it or save/parse it in a .mir file. Make the field const and move the initialization LiveIntervalAnalysis to the MachineRegisterInfo constructor. Also cleanup some code and fix some instances which better use MachineRegisterInfo::subRegLivenessEnabled() instead of TargetSubtargetInfo::enableSubRegLiveness(). llvm-svn: 279676
* GlobalISel: fix cmp test to be in SSA formTim Northover2016-08-241-19/+20
| | | | llvm-svn: 279633
* MIRParser/MIRPrinter: Compute isSSA instead of printing/parsing it.Matthias Braun2016-08-2418-74/+0
| | | | | | | | | Specifying isSSA is an extra line at best and results in invalid MI at worst. Compute the value instead. Differential Revision: http://reviews.llvm.org/D22722 llvm-svn: 279600
* GlobalISel: add some G_TRUNCs to make icmp test valid MIR.Tim Northover2016-08-231-11/+17
| | | | llvm-svn: 279579
* GlobalISel: add forgotten test-case for G_ICMPTim Northover2016-08-231-0/+45
| | | | llvm-svn: 279569
* GlobalISel: make truncate/extend casts uniformTim Northover2016-08-239-43/+43
| | | | | | | They really should have both types represented, but early variants were created before MachineInstrs could have multiple types so they're rather ambiguous. llvm-svn: 279567
* GlobalISel: legalize conditional branches on AArch64.Tim Northover2016-08-231-0/+10
| | | | llvm-svn: 279565
* GlobalISel: mark pointer casts legal on AArch64.Tim Northover2016-08-231-0/+29
| | | | llvm-svn: 279553
* GlobalISel: legalize 1-bit load/store and mark 8/16 bit variants legal on ↵Tim Northover2016-08-231-0/+84
| | | | | | AArch64. llvm-svn: 279548
* BranchRelaxation: Fix handling of blocks with multiple conditionalMatt Arsenault2016-08-231-6/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | branches Looping over all terminators exposed AArch64 tests hitting an assert from analyzeBranch failing. I believe these cases were miscompiled before. e.g. fcmp s0, s1 b.ne LBB0_1 b.vc LBB0_2 b LBB0_2 LBB0_1: ; Large block LBB0_2: ; ... Both of the individual conditional branches need to be expanded, since neither can reach the final block. Split the original block into ones which analyzeBranch will be able to understand. llvm-svn: 279499
* GlobalISel: support legalization of G_FCONSTANTsTim Northover2016-08-191-0/+3
| | | | llvm-svn: 279341
* GlobalISel: teach legalizer how to handle integer constants.Tim Northover2016-08-191-0/+59
| | | | llvm-svn: 279340
* MachineFunction: Cleanup/simplify MachineFunctionProperties::print()Matthias Braun2016-08-191-1/+1
| | | | | | | | | | - Always compile print() regardless of LLVM_ENABLE_DUMP. (We usually only gard dump() functions with that). - Only show the set properties to reduce output clutter. - Remove the unused variant that even shows the unset properties. - Fix comments llvm-svn: 279338
* GlobalISel: translate floating-point round/extendTim Northover2016-08-191-0/+18
| | | | llvm-svn: 279320
* GlobalISel: translate floating-point comparisonsTim Northover2016-08-191-0/+16
| | | | llvm-svn: 279319
* GlobalISel: translate floating-point constantsTim Northover2016-08-191-0/+9
| | | | llvm-svn: 279311
* GlobalISel: translate float/int conversion instructions.Tim Northover2016-08-191-0/+44
| | | | llvm-svn: 279310
* GlobalISel: support translating select instructions.Tim Northover2016-08-191-0/+11
| | | | llvm-svn: 279309
* GlobalISel: translate insertvalue instructions.Tim Northover2016-08-191-0/+25
| | | | | | | | | | This adds a G_INSERT instruction, which technically makes G_SEQUENCE redundant (it's equivalent to a G_INSERT into an IMPLICIT_DEF). We'll leave G_SEQUENCE for now though: it's likely to be far more common as it's a fundamental part of legalization, so avoiding the mess and bloat of the extra IMPLICIT_DEFs is probably worthwhile. llvm-svn: 279306
* GlobalISel: improve representation of G_SEQUENCE and G_EXTRACTTim Northover2016-08-192-20/+20
| | | | | | | | | | | | First, make sure all types involved are represented, rather than being implicit from the register width. Second, canonicalize all types to scalar. These operations just act in bits and don't care about vectors. Also standardize spelling of Indices in the MachineIRBuilder (NFC here). llvm-svn: 279294
* GlobalISel: allow extractvalue to extract an aggregate.Tim Northover2016-08-191-0/+11
| | | | llvm-svn: 279287
* GlobalISel: support translation of extractvalue instructions.Tim Northover2016-08-191-0/+11
| | | | llvm-svn: 279285
* GlobalISel: support overflow arithmetic intrinsics.Tim Northover2016-08-192-8/+94
| | | | | | | | | | | | Unsigned addition and subtraction can reuse the instructions created to legalize large width operations (i.e. both produce and consume a carry flag). Signed operations and multiplies get a dedicated op-with-overflow instruction. Once this is produced the two values are combined into a struct register (which will almost always be merged with a corresponding G_EXTRACT as part of legalization). llvm-svn: 279278
* [CodeGen] Fix a trivial type conversion bug dating back to pre-2008James Molloy2016-08-191-0/+15
| | | | | | | | The heuristic above this code is incredibly suspect, but disregarding that it mutates the cast opcode so we need to check the *mutated* opcode later to see if we need to emit an AssertSext or AssertZext node. Fixes PR29041. llvm-svn: 279223
* AArch64: Don't call getIterator() on iteratorsDuncan P. N. Exon Smith2016-08-181-0/+29
| | | | | | | | | | | | | | | | | Remove an unnecessary round-trip: iterator => operator->() => getIterator() In some cases, the iterator is end(), so the dereference of operator-> is invalid (UB). The testcase only crashes with r278974 (currently reverted to investigate this), which adds an assertion for invalid dereferences of ilist nodes. Fixes PR29035. llvm-svn: 279104
* [AArch64][GlobalISel] Select floating-point binary ops.Ahmed Bougacha2016-08-181-0/+245
| | | | | | There is no FREM instruction, but the others are straightforward. llvm-svn: 279081
* [GlobalISel] Add floating-point binary ops.Ahmed Bougacha2016-08-181-0/+55
| | | | llvm-svn: 279080
* [AArch64][GlobalISel] Select G_SDIV/G_UDIV.Ahmed Bougacha2016-08-181-0/+126
| | | | | | | | There is no REM instruction; that will require an expansion. It's not obvious that should be done in select, rather than as a (custom?) legalization. llvm-svn: 279074
* [GlobalISel] Add support for DIV/REM.Ahmed Bougacha2016-08-181-0/+44
| | | | llvm-svn: 279073
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