summaryrefslogtreecommitdiffstats
path: root/llvm/test/CodeGen/AArch64/shift-mod.ll
Commit message (Collapse)AuthorAgeFilesLines
* [DAGCombiner] try to convert opposing shifts to castsSanjay Patel2019-08-021-6/+4
| | | | | | | | | | | | | | | | | | | | | This reverses a questionable IR canonicalization when a truncate is free: sra (add (shl X, N1C), AddC), N1C --> sext (add (trunc X to (width - N1C)), AddC') https://rise4fun.com/Alive/slRC More details in PR42644: https://bugs.llvm.org/show_bug.cgi?id=42644 I limited this to pre-legalization for code simplicity because that should be enough to reverse the IR patterns. I don't have any evidence (no regression test diffs) that we need to try this later. Differential Revision: https://reviews.llvm.org/D65607 llvm-svn: 367710
* [AArch64][x86] adjust tests with shift-add-shift; NFCSanjay Patel2019-08-011-2/+4
| | | | | | Prevent folding away the math completely. llvm-svn: 367612
* [AArch64][x86] add tests for shift-add-shift; NFC (PR42644)Sanjay Patel2019-08-011-0/+77
| | | | llvm-svn: 367607
* [AArch64] Add patterns for zext/sext of shift amount.Eli Friedman2019-01-221-9/+48
| | | | | | | | | Not sure this is the best fix, but it saves an instruction for certain constructs involving variable shifts. Differential Revision: https://reviews.llvm.org/D55572 llvm-svn: 351768
* [AArch64] Take advantage of variable shift/rotate amount implicit mod operation.Geoff Berry2018-05-241-0/+35
Summary: Optimize code generated for variable shifts/rotates by taking advantage of the implicit and/mod done on the variable shift amount register. Resolves bug 27582 and bug 37421. Reviewers: t.p.northover, qcolombet, MatzeB, javed.absar Subscribers: rengolin, kristof.beyls, mcrosier, llvm-commits Differential Revision: https://reviews.llvm.org/D46844 llvm-svn: 333214
OpenPOWER on IntegriCloud