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* [AARch64] Add Marvell ThunderX3T110 supportWei Zhao2020-06-171-0/+1
| | | | | | | | | | | This is the first checkin to support Marvell ThunderX3T110. Initial definition of the micro-ops of the instructions in ThunderX3T110 is included. Differential Revision: https://reviews.llvm.org/D78129 (cherry picked from commit 382d3a85e2a9269569e7fb8caa487d7ef57900c6)
* [clang][llvm] Obsolete Exynos M1 and M2Evandro Menezes2019-10-301-2/+0
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* [ARM][AArch64] Support for Cortex-A65 & A65AE, Neoverse E1 & N1Pablo Barrio2019-07-251-2/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: Add support for Cortex-A65, Cortex-A65AE, Neoverse E1 and Neoverse N1. Neoverse E1 and Cortex-A65(&AE) only implement the AArch64 state of the Arm architecture. Neoverse N1 implements both AArch32 and AArch64. Cortex-A65: https://developer.arm.com/ip-products/processors/cortex-a/cortex-a65 Cortex-A65AE: https://developer.arm.com/ip-products/processors/cortex-a/cortex-a65ae Neoverse E1: https://developer.arm.com/ip-products/processors/neoverse/neoverse-e1 Neoverse N1: https://developer.arm.com/ip-products/processors/neoverse/neoverse-n1 Patch by Diogo Sampaio and Pablo Barrio Reviewers: samparker, LukeCheeseman, sbaranga, ostannard Reviewed By: ostannard Subscribers: ostannard, javed.absar, kristof.beyls, hiraditya, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D64406 llvm-svn: 367007
* [AArch64, ARM] Add support for Exynos M5Evandro Menezes2019-03-221-0/+1
| | | | | | Add Exynos M5 support and test cases. llvm-svn: 356793
* [AArch64] Support HiSilicon's TSV110 processorBryan Chan2018-11-091-0/+1
| | | | | | | | | | | | Reviewers: t.p.northover, SjoerdMeijer, kristof.beyls Reviewed By: kristof.beyls Subscribers: olista01, javed.absar, kristof.beyls, kristina, llvm-commits Differential Revision: https://reviews.llvm.org/D53908 llvm-svn: 346546
* [AArch64, ARM] Add support for Samsung Exynos M4Evandro Menezes2018-06-061-0/+1
| | | | | | Create a separate feature set for Exynos M4 and add test cases. llvm-svn: 334115
* [AArch64] Add basic support for Qualcomm's Saphira CPU.Chad Rosier2017-09-251-0/+1
| | | | llvm-svn: 314105
* [ARM][AArch64] Cortex-A75 and Cortex-A55 supportSam Parker2017-08-211-1/+3
| | | | | | | | | | | | | | | | | | This patch introduces support for Cortex-A75 and Cortex-A55, Arm's latest big.LITTLE A-class cores. They implement the ARMv8.2-A architecture, including the cryptography and RAS extensions, plus the optional dot product extension. They also implement the RCpc AArch64 extension from ARMv8.3-A. Cortex-A75: https://developer.arm.com/products/processors/cortex-a/cortex-a75 Cortex-A55: https://developer.arm.com/products/processors/cortex-a/cortex-a55 Differential Revision: https://reviews.llvm.org/D36667 llvm-svn: 311316
* [AArch64] Vulcan is now ThunderXT99Joel Jones2017-03-071-1/+1
| | | | | | | | | | | | | | | | | Broadcom Vulcan is now Cavium ThunderX2T99. LLVM Bugzilla: http://bugs.llvm.org/show_bug.cgi?id=32113 Minor fixes for the alignments of loops and functions for ThunderX T81/T83/T88 (better performance). Patch was tested with SpecCPU2006. Patch by Stefan Teleman Differential Revision: https://reviews.llvm.org/D30510 llvm-svn: 297190
* Add support for Samsung Exynos M3 (NFC)Evandro Menezes2016-12-131-0/+1
| | | | llvm-svn: 289613
* [AArch64] Add support for Qualcomm's Falkor CPU.Chad Rosier2016-11-151-0/+1
| | | | | | Differential Revision: https://reviews.llvm.org/D26673 llvm-svn: 287036
* [AArch64] Add support for Samsung Exynos M2 (NFC).Evandro Menezes2016-08-011-0/+1
| | | | llvm-svn: 277364
* [AArch64] Switch regression tests to test features not CPUsSilviu Baranga2016-06-211-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | Summary: We have switched to using features for all heuristics, but the tests for these are still using -mcpu, which means we are not directly testing the features. This converts at least some of the existing regression tests to use the new features. This still leaves the following features untested: merge-narrow-ld predictable-select-expensive alternate-sextload-cvt-f32-pattern disable-latency-sched-heuristic Reviewers: mcrosier, t.p.northover, rengolin Subscribers: MatzeB, aemerson, llvm-commits, rengolin Differential Revision: http://reviews.llvm.org/D21288 llvm-svn: 273271
* [AARCH64] Add support for Broadcom VulcanPankaj Gode2016-06-201-0/+1
| | | | | | | | Adding core tuning support for new Broadcom Vulcan core (ARMv8.1A). Differential Revision: http://reviews.llvm.org/D21500 llvm-svn: 273148
* This adds support for Cortex-A73 as an available target.Sjoerd Meijer2016-06-021-0/+1
| | | | | | Differential Revision: http://reviews.llvm.org/D20865 llvm-svn: 271508
* Fix tests that used CHECK-NEXT-NOT and CHECK-DAG-NOT.Paul Robinson2016-02-261-2/+4
| | | | | | | | FileCheck actually doesn't support combo suffixes. Differential Revision: http://reviews.llvm.org/D17588 llvm-svn: 262054
* [AArch64] Add support for Qualcomm Kryo CPU.Chad Rosier2016-02-121-0/+1
| | | | | | Machine model description by Dave Estes <cestes@codeaurora.org>. llvm-svn: 260686
* [AArch64] Add support for Samsung Exynos-M1MinSeong Kim2016-01-051-0/+1
| | | | | | | | Adds core tuning support for new Samsung Exynos-M1 core (ARMv8-A). Differential Revision: http://reviews.llvm.org/D15663 llvm-svn: 256828
* [AArch64]: Add support for Cortex-A35Christof Douma2015-12-021-0/+1
| | | | | | Adds support for the new Cortex-A35 ARMv8-A core. llvm-svn: 254503
* Adding support to LLVM for targeting Cortex-A72Renato Golin2015-02-041-0/+1
| | | | | | | | | | Currently, Cortex-A72 is modelled as an Cortex-A57 except the fp load balancing pass isn't enabled for Cortex-A72 as it's not profitable to have it enabled for this core. Patch by Ranjeet Singh. llvm-svn: 228140
* Implement AArch64 TTI interface isAsCheapAsAMove.Jiangning Liu2014-07-291-0/+16
llvm-svn: 214159
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