summaryrefslogtreecommitdiffstats
path: root/llvm/test/CodeGen/AArch64/pull-binop-through-shift.ll
Commit message (Collapse)AuthorAgeFilesLines
* [DAGCombiner] visitShiftByConstant(): drop bogus signbit checkRoman Lebedev2019-05-171-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: That check claims that the transform is illegal otherwise. That isn't true: 1. For `ISD::ADD`, we only process `ISD::SHL` outer shift => sign bit does not matter https://rise4fun.com/Alive/K4A 2. For `ISD::AND`, there is no restriction on constants: https://rise4fun.com/Alive/Wy3 3. For `ISD::OR`, there is no restriction on constants: https://rise4fun.com/Alive/GOH 3. For `ISD::XOR`, there is no restriction on constants: https://rise4fun.com/Alive/ml6 So, why is it there then? This changes the testcase that was touched by @spatel in rL347478, but i'm not sure that test tests anything particular? Reviewers: RKSimon, spatel, craig.topper, jojo, rengolin Reviewed By: spatel Subscribers: javed.absar, llvm-commits, spatel Tags: #llvm Differential Revision: https://reviews.llvm.org/D61918 llvm-svn: 361044
* [NFC][CodeGen] Add some more tests for pulling binops through shiftsRoman Lebedev2019-05-161-0/+310
The ashr variant may see relaxation in https://reviews.llvm.org/D61918 llvm-svn: 360881
OpenPOWER on IntegriCloud