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* [AArch64, ARM] Add support for Exynos M5Evandro Menezes2019-03-221-0/+1
| | | | | | Add Exynos M5 support and test cases. llvm-svn: 356793
* [AArch64] Optimize floating point materializationAdhemerval Zanella2019-03-181-0/+15
| | | | | | | | | | | | | | | | | | This patch follows some ideas from r352866 to optimize the floating point materialization even further. It changes isFPImmLegal to considere up to 2 mov instruction or up to 5 in case subtarget has fused literals. The rationale is the cost is the same for mov+fmov vs. adrp+ldr; but the mov+fmov sequence is always better because of the reduced d-cache pressure. The timings are still the same if you consider movw+movk+fmov vs. adrp+ldr will be fused (although one instruction longer). Reviewers: efriedma Differential Revision: https://reviews.llvm.org/D58460 llvm-svn: 356390
* [AArch64, ARM] Add support for Samsung Exynos M4Evandro Menezes2018-06-061-0/+1
| | | | | | Create a separate feature set for Exynos M4 and add test cases. llvm-svn: 334115
* [AArch64] Add pipeline model for Exynos M3Evandro Menezes2018-01-301-0/+1
| | | | | | | | Add the scheduling and cost model for Exynos M3. Differential revision: https://reviews.llvm.org/D42387 llvm-svn: 323773
* [AArch64] Add test case for fusion of literal generationEvandro Menezes2017-02-211-0/+46
Add test case from https://reviews.llvm.org/D28698 that was somehow lost in transit. llvm-svn: 295775
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