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* [SelectionDAG] Add fcmp UNDEF handling to SelectionDAG::FoldSetCCSimon Pilgrim2019-04-051-7/+10
| | | | | | | | | | Second half of PR40800, this patch adds DAG undef handling to fcmp instructions to match the behavior in llvm::ConstantFoldCompareInstruction, this permits constant folding of vector comparisons where some elements had been reduced to UNDEF (by SimplifyDemandedVectorElts etc.). This involves a lot of tweaking to reduced tests as bugpoint loves to reduce fcmp arguments to undef........ Differential Revision: https://reviews.llvm.org/D60006 llvm-svn: 357765
* [AArch64] Regenerate half precision testsSimon Pilgrim2019-03-291-24/+51
| | | | | | Prep work for PR40800 (Add UNDEF handling to SelectionDAG::FoldSetCC) llvm-svn: 357286
* DAG combiner: fold (select, C, X, undef) -> XStanislav Mekhanoshin2018-11-161-2/+2
| | | | | | Differential Revision: https://reviews.llvm.org/D54646 llvm-svn: 347110
* [AArch64] Fix DAG selection for cmps for fp16 typeWeiming Zhao2016-05-111-0/+12
| | | | | | | | | | | | Summary: When emitting comparison for fp16, in addition to promote the LHS and RHS to fp32, we need to change the VT as well. Reviewers: t.p.northover Subscribers: t.p.northover, aemerson, rengolin, llvm-commits Differential Revision: http://reviews.llvm.org/D19922 llvm-svn: 269151
* [opaque pointer type] Add textual IR support for explicit type parameter to ↵David Blaikie2015-02-271-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | load instruction Essentially the same as the GEP change in r230786. A similar migration script can be used to update test cases, though a few more test case improvements/changes were required this time around: (r229269-r229278) import fileinput import sys import re pat = re.compile(r"((?:=|:|^)\s*load (?:atomic )?(?:volatile )?(.*?))(| addrspace\(\d+\) *)\*($| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$)") for line in sys.stdin: sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line)) Reviewers: rafael, dexonsmith, grosser Differential Revision: http://reviews.llvm.org/D7649 llvm-svn: 230794
* AArch64: implement efficient f16 bitcastsTim Northover2014-07-181-0/+21
| | | | | | | | Because i16 is illegal, there's no native DAG method to represent a bitcast to or from an f16 type. This meant LLVM was inserting a stack store/load pair which is really not ideal. llvm-svn: 213378
* AArch64: support f16 extend/trunc operations.Tim Northover2014-07-181-0/+36
| | | | llvm-svn: 213375
* CodeGen: soften f16 type by default instead of marking legal.Tim Northover2014-07-181-0/+26
Actual support for softening f16 operations is still limited, and can be added when it's needed. But Soften is much closer to being a useful thing to try than keeping it Legal when no registers can actually hold such values. Longer term, we probably want something between Soften and Promote semantics for most targets, it'll be more efficient to promote the 4 basic operations to f32 than libcall them. llvm-svn: 213372
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