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path: root/llvm/test/CodeGen/AArch64/fast-isel-branch-cond-mask.ll
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* Relax fast register allocator related test cases; NFCMatthias Braun2018-10-291-2/+2
| | | | | | | | | | | | | - Relex hard coded registers and stack frame sizes - Some test cleanups - Change phi-dbg.ll to match on mir output after phi elimination instead of going through the whole codegen pipeline. This is in preparation for https://reviews.llvm.org/D52010 I'm committing all the test changes upfront that work before and after independently. llvm-svn: 345532
* AArch64FastISel: Use cbz/cbnz to branch on i1Matthias Braun2015-12-031-2/+1
| | | | | | | | | In the case of a conditional branch without a preceding cmp we used to emit a "and; cmp; b.eq/b.ne" sequence, use tbz/tbnz instead. Differential Revision: http://reviews.llvm.org/D15122 llvm-svn: 254621
* [AArch64][FastISel] Always use AND before checking the branch flag.Juergen Ributzka2015-08-061-0/+20
When we are not emitting the condition for the branch, because the condition is in another BB or SDAG did the selection for us, then we have to mask the flag in the register with AND. This is required when the condition comes from a truncate, because SDAG only truncates down to a legal size of i32. This fixes rdar://problem/22161062. llvm-svn: 244291
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