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* [DAGCombiner] exclude x*2.0 from normal negation profitability rulesSanjay Patel2019-08-091-6/+4
| | | | | | | | | | | | | | | | | | | | | | | This is the codegen part of fixing: https://bugs.llvm.org/show_bug.cgi?id=32939 Even with the optimal/canonical IR that is ideally created by D65954, we would reverse that transform in DAGCombiner and end up with the same asm on AArch64 or x86. I see 2 options for trying to correct this: 1. Limit isNegatibleForFree() by special-casing the fmul pattern (this patch). 2. Avoid creating (fmul X, 2.0) in the 1st place by adding a special-case transform to SelectionDAG::getNode() and/or SelectionDAGBuilder::visitFMul() that matches the transform done by DAGCombiner. This seems like the less intrusive patch, but if there's some other reason to prefer 1 option over the other, we can change to the other option. Differential Revision: https://reviews.llvm.org/D66016 llvm-svn: 368490
* [AArch64][x86] add tests for pessimization of expression with X*2.0 ↵Sanjay Patel2019-08-091-0/+30
| | | | | | (PR32939); NFC llvm-svn: 368445
* Migrate some more fadd and fsub cases away from UnsafeFPMath control to ↵Michael Berg2019-07-311-15/+10
| | | | | | | | | | | | | | | | utilize NoSignedZerosFPMath options control Summary: Honoring no signed zeroes is also available as a user control through clang separately regardless of fastmath or UnsafeFPMath context, DAG guards should reflect this context. Reviewers: spatel, arsenm, hfinkel, wristow, craig.topper Reviewed By: spatel Subscribers: rampitec, foad, nhaehnle, wuzish, nemanjai, jvesely, wdng, javed.absar, MaskRay, jsji Differential Revision: https://reviews.llvm.org/D65170 llvm-svn: 367486
* [AArch64] Optimize floating point materializationAdhemerval Zanella2019-02-011-14/+14
| | | | | | | | | | | | | | | This patch changes isFPImmLegal to return if the value can be enconded as the immediate operand of a logical instruction besides checking if for immediate field for fmov. This optimizes some floating point materization, inclusive values used on isinf lowering. Reviewed By: rengolin, efriedma, evandro Differential Revision: https://reviews.llvm.org/D57044 llvm-svn: 352866
* [DAGCombiner] allow undef elts in vector fmul matchingSanjay Patel2018-10-151-6/+4
| | | | llvm-svn: 344534
* [AArch64] add tests for fmul x, -2.0 with undef elts; NFCSanjay Patel2018-10-151-10/+45
| | | | | | Also, add tests with commuted operands. There was no coverage for that case. llvm-svn: 344531
* Utilize new SDNode flag functionality to expand current support for faddMichael Berg2018-06-181-3/+4
| | | | | | | | | | | | | | Summary: This patch originated from D46562 and is a proper subset, with some issues addressed. Reviewers: spatel, hfinkel, wristow, arsenm, javed.absar Reviewed By: spatel Subscribers: wdng, nhaehnle Differential Revision: https://reviews.llvm.org/D47909 llvm-svn: 334996
* [DAGCombiner] remove hasOneUse() check from fadd constants transformSanjay Patel2018-06-131-3/+8
| | | | | | | | | | | We're constant folding here, so we shouldn't check uses. This matches the IR optimizer behavior. The x86 test shows the expected win. The AArch64 test shows something else. This only seems to happen if the "generic" AArch64 CPU model is used by MachineCombiner, so I'll file a bug report to follow-up. llvm-svn: 334608
* [AArch64] add tests for fadd with more than one use; NFCSanjay Patel2018-06-121-27/+83
| | | | llvm-svn: 334556
* [DAGCombine] Transform (fadd A, (fmul B, -2.0)) -> (fsub A, (fadd B, B)).Chad Rosier2017-05-041-0/+78
Differential Revision: http://reviews.llvm.org/D32596 llvm-svn: 302153
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