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* [AArch64] match splat of bitcasted extract subvector to DUPLANESanjay Patel2019-12-221-8/+8
| | | | | | | | | | This is another potential regression exposed by D63815. Here we peek through a bitcast to find an extract subvector and scale the splat offset based on that: splat (bitcast (extract X, C)), LaneC --> duplane (bitcast X), LaneC' Differential Revision: https://reviews.llvm.org/D71672
* [AArch64] add more tests for extract-bitcast-splat; NFCSanjay Patel2019-12-201-2/+44
| | | | | Goes with D71672 - we should be able to handle casting to a wider type as well as casting to a narrower type.
* [AArch64] add tests for bitcasted DUPLANE; NFCSanjay Patel2019-12-181-0/+40
| | | | See D63815 for context/motivation.
* [AArch64] update test checks; NFCSanjay Patel2019-12-181-491/+221
| | | | | The common prefix reduces a bunch of replication; not sure why it didn't happen before.
* [clang][llvm] Obsolete Exynos M1 and M2Evandro Menezes2019-10-301-348/+0
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* [AArch64] Regenerate 2velem tests. NFCI.Simon Pilgrim2019-06-241-479/+1622
| | | | | | Prep work for an upcoming patch llvm-svn: 364204
* [Codegen] fix typos in test caseXing GUO2019-03-021-3/+3
| | | | llvm-svn: 355264
* [AArch64] Update test cases for Exynos M3Evandro Menezes2018-01-301-0/+59
| | | | | | Update any test case relevant for Exynos M3. llvm-svn: 323775
* [AArch64] Expand test coverage of vector element shuffling to ExynosEvandro Menezes2017-12-181-534/+151
| | | | | | Make sure that all test cases are run for Exynos as well. Otherwise, NFC. llvm-svn: 321032
* [AArch64] Avoid SIMD interleaved store instruction for Exynos.Abderrazek Zaafrani2017-12-081-0/+21
| | | | | | | Replace interleaved store instructions by equivalent and more efficient instructions based on latency cost model. Https://reviews.llvm.org/D38196 llvm-svn: 320123
* [AArch64] Avoid generating indexed vector instructions for ExynosSebastian Pop2016-10-081-0/+241
| | | | | | | | | | | | | | | | | | Avoid generating indexed vector instructions for Exynos. This is needed for fmla/fmls/fmul/fmulx. For example, the instruction fmla v0.4s, v1.4s, v2.s[1] is less efficient than the instructions dup v2.4s, v2.s[1] fmla v0.4s, v1.4s, v2.4s Patch written by Abderrazek Zaafrani. Differential Revision: https://reviews.llvm.org/D21571 llvm-svn: 283663
* [AArch64] Fix FMLS scalar-indexed-from-2s-after-neg patterns.Ahmed Bougacha2015-08-141-0/+55
| | | | | | | | | We canonicalize V64 vectors to V128 through insert_subvector: the other FMLA/FMLS/FMUL/FMULX patterns match that already, but this one doesn't, so we'd fail to match fmls and generate fneg+fmla instead. The vector equivalents are already tested and functional. llvm-svn: 245107
* AArch64/ARM64: move ARM64 into AArch64's placeTim Northover2014-05-241-0/+2853
This commit starts with a "git mv ARM64 AArch64" and continues out from there, renaming the C++ classes, intrinsics, and other target-local objects for consistency. "ARM64" test directories are also moved, and tests that began their life in ARM64 use an arm64 triple, those from AArch64 use an aarch64 triple. Both should be equivalent though. This finishes the AArch64 merge, and everyone should feel free to continue committing as normal now. llvm-svn: 209577
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