Commit message (Expand) | Author | Age | Files | Lines | |
---|---|---|---|---|---|
* | [DAGCombiner] Set the right SDLoc on a newly-created sextload (6/N) | Vedant Kumar | 2018-05-11 | 1 | -6/+6 |
* | [DAGCombiner] Set the right SDLoc on a newly-created zextload (1/N) | Vedant Kumar | 2018-05-01 | 1 | -6/+6 |
* | [AArch64] Update test cases for Exynos M3 | Evandro Menezes | 2018-01-30 | 1 | -34/+35 |
* | [CodeGen] Use MachineOperand::print in the MIRPrinter for MO_Register. | Francis Visoiu Mistrih | 2017-12-07 | 1 | -26/+26 |
* | [CodeGen] Unify MBB reference format in both MIR and debug output | Francis Visoiu Mistrih | 2017-12-04 | 1 | -14/+14 |
* | [CodeGen] Print "%vreg0" as "%0" in both MIR and debug output | Francis Visoiu Mistrih | 2017-11-30 | 1 | -26/+26 |
* | CodeGen: Rename DEBUG_TYPE to match passnames | Matthias Braun | 2017-05-25 | 1 | -2/+2 |
* | [MachineScheduler]Add support for store clustering | Jun Bum Lim | 2016-04-15 | 1 | -14/+14 |
* | [AArch64] Disable LDP/STP for quads | Evandro Menezes | 2016-04-13 | 1 | -0/+51 |
* | [AArch64] Enable more load clustering in the MI Scheduler. | Chad Rosier | 2016-03-18 | 1 | -0/+99 |