summaryrefslogtreecommitdiffstats
path: root/llvm/test/CodeGen/AArch64/GlobalISel/select-implicit-def.mir
Commit message (Collapse)AuthorAgeFilesLines
* [globalisel] Remove redundant -global-isel option from tests that use ↵Daniel Sanders2018-05-051-1/+1
| | | | | | | | | | | -run-pass. NFC As Roman Tereshin pointed out in https://reviews.llvm.org/D45541, the -global-isel option is redundant when -run-pass is given. -global-isel sets up the GlobalISel passes in the pass manager but -run-pass skips that entirely and configures it's own pipeline. llvm-svn: 331603
* [AArch64][GlobalISel] Fix old use of % sigil in test.Amara Emerson2018-02-021-2/+2
| | | | | | My rebase had missed the new $ sigil we're using. llvm-svn: 324051
* [GlobalISel] Constrain the dest reg of IMPLICT_DEF.Amara Emerson2018-02-021-0/+19
| | | | | | | | | | This fixes a crash where the user is a COPY, which deliberately does not constrain its source operands, resulting in a vreg without a reg class escaping selection. Differential Revision: https://reviews.llvm.org/D42697 llvm-svn: 324047
* Followup on Proposal to move MIR physical register namespace to '$' sigil.Puyan Lotfi2018-01-311-2/+2
| | | | | | | | | | | | Discussed here: http://lists.llvm.org/pipermail/llvm-dev/2018-January/120320.html In preparation for adding support for named vregs we are changing the sigil for physical registers in MIR to '$' from '%'. This will prevent name clashes of named physical register with named vregs. llvm-svn: 323922
* MIR: Print the register class or bank in vreg defsJustin Bogner2017-10-241-5/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | This updates the MIRPrinter to include the regclass when printing virtual register defs, which is already valid syntax for the parser. That is, given 64 bit %0 and %1 in a "gpr" regbank, %1(s64) = COPY %0(s64) would now be written as %1:gpr(s64) = COPY %0(s64) While this change alone introduces a bit of redundancy with the registers block, it allows us to update the tests to be more concise and understandable and brings us closer to being able to remove the registers block completely. Note: We generally only print the class in defs, but there is one exception. If there are uses without any defs whatsoever, we'll print the class on all uses. I'm not completely convinced this comes up in meaningful machine IR, but for now the MIRParser and MachineVerifier both accept that kind of stuff, so we don't want to have a situation where we can print something we can't parse. llvm-svn: 316479
* GISel: Canonicalize select tests using update_mir_test_checksJustin Bogner2017-10-181-8/+8
| | | | | | | | This runs `udpate_mir_test_checks --add-vreg-checks` on the tests taht are already more or less in the format that generates, so that there will be less churn in some upcoming changes. llvm-svn: 316139
* GlobalISel: Handle selection of G_IMPLICIT_DEF in AArch64Justin Bogner2017-07-121-0/+30
A generic variant of IMPLICIT_DEF was added in r306875, but this survives to selection and hits a `Cannot Select`. Add handling that converts the note to a regular IMPLICIT_DEF. llvm-svn: 307817
OpenPOWER on IntegriCloud