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* [Alignment] Use llvm::Align in MachineFunction and TargetLowering - fixes ↵Guillaume Chatelet2019-09-111-2/+2
| | | | | | | | | | | | | | | | | | | | | | mir parsing Summary: This catches malformed mir files which specify alignment as log2 instead of pow2. See https://reviews.llvm.org/D65945 for reference, This is patch is part of a series to introduce an Alignment type. See this thread for context: http://lists.llvm.org/pipermail/llvm-dev/2019-July/133851.html See this patch for the introduction of the type: https://reviews.llvm.org/D64790 Reviewers: courbet Subscribers: MatzeB, qcolombet, dschuff, arsenm, sdardis, nemanjai, jvesely, nhaehnle, hiraditya, kbarton, asb, rbar, johnrusso, simoncook, apazos, sabuasal, niosHD, jrtc27, MaskRay, zzheng, edward-jones, atanasyan, rogfer01, MartinMosbeck, brucehoult, the_o, PkmX, jocewei, jsji, Petar.Avramovic, asbirlea, s.egerton, pzheng, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D67433 llvm-svn: 371608
* Recommit "[GlobalISel] Import patterns containing INSERT_SUBREG"Jessica Paquette2019-08-271-10/+16
| | | | | | | | | | I thought `llvm::sort` was stable for some reason but it's not. Use `llvm::stable_sort` in `CodeGenTarget::getSuperRegForSubReg`. Original patch: https://reviews.llvm.org/D66498 llvm-svn: 370084
* Revert "[GlobalISel] Import patterns containing INSERT_SUBREG"Jessica Paquette2019-08-271-16/+10
| | | | | | | | | | When EXPENSIVE_CHECKS are enabled, GlobalISelEmitterSubreg.td doesn't get stable output. Reverting while I debug it. See: https://reviews.llvm.org/D66498 llvm-svn: 370080
* [GlobalISel] Import patterns containing INSERT_SUBREGJessica Paquette2019-08-261-10/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This teaches the importer to handle INSERT_SUBREG instructions. We were missing patterns involving INSERT_SUBREG in AArch64. It appears in AArch64InstrInfo.td 107 times, and 14 times in AArch64InstrFormats.td. To meaningfully import it, the GlobalISelEmitter needs to know how to infer a super register class for a given register class. This patch introduces the following: - `getSuperRegForSubReg`, a function which finds the largest register class which supports a value type and subregister index - `inferSuperRegisterClass`, a function which finds the appropriate super register class for an INSERT_SUBREG' - `inferRegClassFromPattern`, a function which allows for some trivial lookthrough into instructions - `getRegClassFromLeaf`, a helper function which returns the register class for a leaf `TreePatternNode` - Support for subregister index operands in `importExplicitUseRenderer` It also - Updates tests in each backend which are impacted by the change - Adds GlobalISelEmitterSubreg.td to test that we import and skip the expected patterns As a result of this patch, INSERT_SUBREG patterns in X86 may use the LOW32_ADDR_ACCESS_RBP register class instead of GR32. This is correct, since the register class contains the same registers as GR32 (except with the addition of RBP). So, this also teaches X86 to handle that register class. This is in line with X86ISelLowering, which treats this as a GR class. Differential Revision: https://reviews.llvm.org/D66498 llvm-svn: 369973
* [AArch64][GlobalISel] Add some support for G_CONCAT_VECTORS.Amara Emerson2019-03-141-0/+63
Handles concatenating 2 x v2s32 and 2 x v4s16 Differential Revision: https://reviews.llvm.org/D59390 llvm-svn: 356212
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