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* Silence warnings of a mysterious compiler that still defaults to C89.Benjamin Kramer2012-01-041-2/+2
| | | | llvm-svn: 147553
* use getHostTriple instead of getDefaultTargetTriple in getClosestTargetForJITSebastian Pop2012-01-044-7/+18
| | | | | | | | | | Get back getHostTriple. For JIT compilation, use the host triple instead of the default target: this fixes some JIT testcases that used to fail when the compiler has been configured as a cross compiler. llvm-svn: 147542
* Enable -soft-float for MIPS.Akira Hatanaka2012-01-041-7/+10
| | | | llvm-svn: 147541
* Remove pointless asserts.Nick Lewycky2012-01-041-2/+0
| | | | llvm-svn: 147529
* Teach instcombine all sorts of great stuff about shifts that have exact, nuw orNick Lewycky2012-01-042-8/+59
| | | | | | nsw bits on them. llvm-svn: 147528
* Allow vector shuffle normalizing to use concat vector even if the sources ↵Craig Topper2012-01-041-11/+24
| | | | | | are commuted in the shuffle mask. llvm-svn: 147527
* Implement VECTOR_SHUFFLE canonicalizations during DAG combine.Craig Topper2012-01-041-2/+50
| | | | llvm-svn: 147525
* Rename immLUiOpnd.Akira Hatanaka2012-01-042-3/+3
| | | | llvm-svn: 147519
* - Define base classes for Jump-and-link instructions and make 32-bit and 64-bitAkira Hatanaka2012-01-042-42/+27
| | | | | | | | | versions derive from them. - JALR64 is not needed since N64 does not emit jal. - Add template parameter to BranchLink that sets the rt field. - Fix the set of temporary registers for O32 and N64. llvm-svn: 147518
* Have getRegForInlineAsmConstraint return the correct register class when targetAkira Hatanaka2012-01-041-4/+9
| | | | | | is Mips64. llvm-svn: 147516
* Fix more places which should be checking for iOS, not darwin.Evan Cheng2012-01-043-18/+18
| | | | llvm-svn: 147513
* For x86, canonicalize maxEvan Cheng2012-01-041-0/+31
| | | | | | | | | | | | | | | | | | | | | | | | | | (x > y) ? x : y => (x >= y) ? x : y So for something like (x - y) > 0 : (x - y) ? 0 It will be (x - y) >= 0 : (x - y) ? 0 This makes is possible to test sign-bit and eliminate a comparison against zero. e.g. subl %esi, %edi testl %edi, %edi movl $0, %eax cmovgl %edi, %eax => xorl %eax, %eax subl %esi, $edi cmovsl %eax, %edi rdar://10633221 llvm-svn: 147512
* Turn a few more inline asm errors into "emitErrors" instead of fatal errors.Chris Lattner2012-01-031-9/+21
| | | | | | | | | | | | | | | | | | Before we'd get: $ clang t.c fatal error: error in backend: Invalid operand for inline asm constraint 'i'! Now we get: $ clang t.c t.c:16:5: error: invalid operand for inline asm constraint 'i'! "movq (%4), %%mm0\n" ^ Which at least gets us the inline asm that is the problem. llvm-svn: 147502
* generalize LLVMContext::emitError to take a twine instead of a StringRef.Chris Lattner2012-01-031-3/+3
| | | | llvm-svn: 147501
* Fix 80-column violations.Chad Rosier2012-01-031-4/+5
| | | | llvm-svn: 147495
* Revert r146997, "Heed spill slot alignment on ARM."Jakob Stoklund Olesen2012-01-032-4/+3
| | | | | | | | | This patch caused a miscompilation of oggenc because a frame pointer was suddenly needed halfway through register allocation. <rdar://problem/10625436> llvm-svn: 147487
* Assert when reserved registers have been assigned.Jakob Stoklund Olesen2012-01-031-0/+4
| | | | | | | | | This can only happen if the set of reserved registers changes during register allocation. <rdar://problem/10625436> llvm-svn: 147486
* Revert 147426 because it caused pr11696.Nadav Rotem2012-01-031-18/+0
| | | | llvm-svn: 147485
* Fix incorrect widening of the bitcast sdnode in case the incoming operand is ↵Nadav Rotem2012-01-031-0/+6
| | | | | | integer-promoted. llvm-svn: 147484
* Enhance DAGCombine for transforming 128->256 casts into a vmovaps, ratherChad Rosier2012-01-032-0/+19
| | | | | | | then a vxorps + vinsertf128 pair if the original vector came from a load. rdar://10594409 llvm-svn: 147481
* Conform to the style guide; remove 'else' after 'return'. Also remove an extraNick Lewycky2012-01-031-56/+36
| | | | | | if-statement by turning it into an assert. No functionality change. llvm-svn: 147474
* Remove the restriction that target intrinsics can only involve legal types. ↵Owen Anderson2012-01-031-8/+0
| | | | | | Targets can perfects well support intrinsics on illegal types, as long as they are prepared to perform custom expansion during type legalization. For example, a target where i64 is illegal might still support the i64 intrinsic operation using pairs of i32's. ARM already does some expansions like this for non-intrinsic operations. llvm-svn: 147472
* Clarified assert text.Lang Hames2012-01-031-1/+1
| | | | llvm-svn: 147471
* Fix malformed assert.Matt Beaumont-Gay2012-01-031-1/+1
| | | | | | | | If anybody has strong feelings about 'default: assert(0 && "blah")' vs 'default: llvm_unreachable("blah")', feel free to regularize the instances of each in this file. llvm-svn: 147459
* Fix typo in ruler. No functionality change.Nick Lewycky2012-01-031-1/+1
| | | | llvm-svn: 147454
* Intel style asm variant does not need '%' prefix.Devang Patel2012-01-032-28/+28
| | | | llvm-svn: 147453
* Type: replaced usage of ID with getTypeID().Stepan Dyatkovskiy2012-01-031-11/+12
| | | | llvm-svn: 147446
* Fixed a bug in SelectionDAG.cpp.Elena Demikhovsky2012-01-031-6/+50
| | | | | | | | | | | | The failure seen on win32, when i64 type is illegal. It happens on stage of conversion VECTOR_SHUFFLE to BUILD_VECTOR. The failure message is: llc: SelectionDAG.cpp:784: void VerifyNodeCommon(llvm::SDNode*): Assertion `(I->getValueType() == EltVT || (EltVT.isInteger() && I->getValueType().isInteger() && EltVT.bitsLE(I->getValueType()))) && "Wrong operand type!"' failed. I added a special test that checks vector shuffle on win32. llvm-svn: 147445
* Fix SCEVExpander to handle loops with no preheader when LSR gives it aAndrew Trick2012-01-021-0/+6
| | | | | | | | "phony" insertion point. Fixes rdar://10619599: "SelectionDAGBuilder shouldn't visit PHI nodes!" assert llvm-svn: 147439
* Miscellaneous shuffle lowering cleanup. No functional changes. Primarily ↵Craig Topper2012-01-021-47/+43
| | | | | | converting the indexing loops to unsigned to be consistent across functions. llvm-svn: 147430
* Make CanXFormVExtractWithShuffleIntoLoad reject loads with multiple uses. ↵Craig Topper2012-01-022-26/+22
| | | | | | Also make it return false if there's not even a load at all. This makes the code better match the code in DAGCombiner that it tries to match. These two changes prevent some cases where vector_shuffles were making it to instruction selection and causing the older shuffle selection code to be triggered. Also needed to fix a bad pattern that this change exposed. This is the first step towards getting rid of the old shuffle selection support. No test cases yet because there's no way to tell whether a shuffle was handled in the legalize stage or at instruction selection. llvm-svn: 147428
* Optimize the sequence blend(sign_extend(x)) to blend(shl(x)) since SSE blend ↵Nadav Rotem2012-01-021-0/+18
| | | | | | instructions only look at the highest bit. llvm-svn: 147426
* Materialize functions whose basic blocks are used by global variables. FixesRafael Espindola2012-01-022-1/+13
| | | | | | PR11677. llvm-svn: 147425
* Allow CRC32 instructions to be selected when AVX is enabled.Craig Topper2012-01-012-2/+3
| | | | llvm-svn: 147411
* Fix sfence, lfence, mfence, and clflush to be able to be selected when AVX ↵Craig Topper2012-01-013-20/+21
| | | | | | is enabled. Fix monitor and mwait to require SSE3 or AVX, previously they worked even if SSE3 was disabled. Make prefetch instructions not set the execution domain since they don't use XMM registers. llvm-svn: 147409
* X86Disassembler: Fix undefined behavior found by GCC 4.6Benjamin Kramer2012-01-011-3/+5
| | | | llvm-svn: 147404
* PatternMatch: Introduce a matcher for instructions with the "exact" bit. Use ↵Benjamin Kramer2012-01-012-19/+10
| | | | | | it to simplify a few matchers. llvm-svn: 147403
* Revert 147399. It broke CodeGen/ARM/vext.ll.Rafael Espindola2012-01-011-39/+5
| | | | llvm-svn: 147400
* Fixed a bug in SelectionDAG.cpp.Elena Demikhovsky2012-01-011-5/+39
| | | | | | | | | | | | The failure seen on win32, when i64 type is illegal. It happens on stage of conversion VECTOR_SHUFFLE to BUILD_VECTOR. The failure message is: llc: SelectionDAG.cpp:784: void VerifyNodeCommon(llvm::SDNode*): Assertion `(I->getValueType() == EltVT || (EltVT.isInteger() && I->getValueType().isInteger() && EltVT.bitsLE(I->getValueType()))) && "Wrong operand type!"' failed. I added a special test that checks vector shuffle on win32. llvm-svn: 147399
* Merge X86 SHUFPS and SHUFPD node types.Craig Topper2011-12-314-58/+35
| | | | llvm-svn: 147394
* Add patterns for integer forms of SHUFPD/VSHUFPD with a memory load.Craig Topper2011-12-311-0/+6
| | | | llvm-svn: 147393
* Fix typo in a SHUFPD and VSHUFPD pattern that prevented SHUFPD/VSHUFPD with ↵Craig Topper2011-12-311-2/+2
| | | | | | a load from being selected. llvm-svn: 147392
* Make use of the exact bit when optimizing '(X >>exact 3) << 1' to eliminate theNick Lewycky2011-12-311-5/+11
| | | | | | | 'and' that would zero out the trailing bits, and to produce an exact shift ourselves. llvm-svn: 147391
* VMCore: add assert for miscompileDylan Noblesmith2011-12-311-0/+5
| | | | | | | | | | | See PR11652. Trying to add this assert to setSubclassData() itself actually prevented the miscompile entirely, so it has to be here. This makes the source of the bug more obvious than the other asserts triggering later on did. llvm-svn: 147390
* Cleanup Mips code and rename some variables. Patch by Jack CarterBruno Cardoso Lopes2011-12-304-171/+79
| | | | llvm-svn: 147383
* Improve Mips JIT.Bruno Cardoso Lopes2011-12-303-6/+15
| | | | | | | | | | | Implement encoder methods getJumpTargetOpValue and getBranchTargetOpValue for jmptarget and brtarget Mips tablegen operand types in the code emitter for old-style JIT. Rename the pc relative relocation for branches - new name is Mips::reloc_mips_pc16. Patch by Sasa Stankovic llvm-svn: 147382
* Make FMA4 imply AVX so that YMM registers would be available. Necessitates ↵Craig Topper2011-12-301-6/+8
| | | | | | removing from Bulldozer CPU types since it would enable AVX code generation implicitly. Also make SSE4A imply SSE3. Without some level of SSE implied, XMM registers wouldn't be legal. llvm-svn: 147369
* Add disassembler support for VPERMIL2PD and VPERMIL2PS.Craig Topper2011-12-302-4/+12
| | | | llvm-svn: 147368
* Add FMA4 instructions to disassembler.Craig Topper2011-12-301-38/+53
| | | | llvm-svn: 147367
* Separate the concept of having memory access in operand 4 from the concept ↵Craig Topper2011-12-305-34/+26
| | | | | | of having the W bit set for XOP instructons. Removes ORing W-bits in the encoder and will similarly simplify the disassembler implementation. llvm-svn: 147366
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