Revert 147426 because it caused pr11696.

llvm-svn: 147485

1 files changed, 0 insertions, 18 deletions

diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp
index 47b80d036e5..74ae8a85bda 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -13139,24 +13139,6 @@ static SDValue PerformSELECTCombine(SDNode *N, SelectionDAG &DAG,
       }
   }
 
-  // The VSELECT instruction is lowered to SSE blend instructions. In many cases
-  // the mask is sign-extended to fill the entire lane. However, we only care
-  // for the highest bit. Convert sign_extend to srl because it is cheaper.
-  // (vselect(sign_extend(x))) ->  vselect(srl(x))
-  if (N->getOpcode() == ISD::VSELECT &&
-      Cond.getOpcode() == ISD::SIGN_EXTEND_INREG && Cond.hasOneUse()) {
-    EVT CondVT = Cond.getValueType();
-    EVT SExtTy = cast<VTSDNode>(Cond.getOperand(1))->getVT();
-    unsigned BitsDiff = CondVT.getScalarType().getSizeInBits() -
-                        SExtTy.getScalarType().getSizeInBits();
-
-    EVT ShiftType = EVT::getVectorVT(*DAG.getContext(),
-                MVT::i32, CondVT.getVectorNumElements());
-    SDValue SHL = DAG.getNode(ISD::SHL, DL, CondVT, Cond.getOperand(0),
-                DAG.getConstant(BitsDiff, ShiftType));
-    return DAG.getNode(ISD::VSELECT, DL, VT, SHL, LHS, RHS);
-  }
-
   return SDValue();
 }