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* MachineScheduler: Followup to debug message changesMatthias Braun2016-06-231-1/+0
| | | | | | | Do not dump intermediate state of the pending queue anymore now that we always dump the final state before picking. llvm-svn: 273618
* Codegen: [X86] preservere memory refs for folded umul_lohiKyle Butt2016-06-231-2/+10
| | | | | | | | | Memory references were not being propagated for this folded load. This prevented optimizations like LICM from hoisting the load. Added test to verify that this allows LICM to proceed. llvm-svn: 273617
* Codegen: LICM Remove check for exactly 1 register def.Kyle Butt2016-06-231-1/+0
| | | | | | | | | | | | | | | | | | When considering whether to split an instruction with a memory operand into an explicit load and a register-based instruction, we currently check that the resulting instruction has exactly 1 def. This prevents 2 important LICM optimizations: compares with memory operands, and double indirect calls. All the tests and the test-suite pass without the check. My guess as to original intent is to limit the additional register pressure created by the new instruction, but given that we only split out a single register, it is already limited. The licm-dominance test now checks actual memory loads for hoisting instead of undef, and it tests compares. hoist-invariant-load.ll now checks for 2 hoists, the intended hoist, and a bonus from calling a got-relative function in a loop. llvm-svn: 273616
* MachineScheduler: Improve debug messagesMatthias Braun2016-06-231-7/+7
| | | | | | | Consistenly display available and pending queues immediately before the scheduling choice is done. llvm-svn: 273615
* Uses shouldAssumeDSOLocal.Rafael Espindola2016-06-231-10/+2
| | | | | | With that SystemZ knows to avoid a GOT for PIE. llvm-svn: 273614
* Attempt #2 to unbreak bots broken by r273596.George Burgess IV2016-06-232-4/+4
| | | | | | | | Some of the bots running GCC 4.7 seem to be having trouble with lambdas that explicitly capture `this`. Relevant-looking bug: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=53137 llvm-svn: 273613
* Refactor to use shouldAssumeDSOLocal. NFC.Rafael Espindola2016-06-231-10/+14
| | | | llvm-svn: 273612
* [libfuzzer] moving is_ascii handler inside mutation dispatcher.Mike Aizatsky2016-06-236-60/+65
| | | | | | | | Summary: It also fixes a bug, when first random might not be ascii. Differential Revision: http://reviews.llvm.org/D21573 llvm-svn: 273611
* InstCombine rule to fold trunc when value availableAnna Thomas2016-06-232-21/+82
| | | | | | | | | | | | | | Summary: This instcombine rule folds away trunc operations that have value available from a prior load or store. This kind of code can be generated as a result of GVN widening the load or from source code as well. Reviewers: reames, majnemer, sanjoy Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D21246 llvm-svn: 273608
* AMDGPU: Add option to disable spilling SGPRs to VGPRs.Matt Arsenault2016-06-231-2/+9
| | | | | | This can help debug spilling problems. llvm-svn: 273605
* Attempt to fix breakage caused by r273596.George Burgess IV2016-06-231-3/+3
| | | | llvm-svn: 273601
* [CFLAA] Use better interprocedural function summaries.George Burgess IV2016-06-232-92/+130
| | | | | | | | | | | | | Previously, we just unified any arguments that seemed to be related to each other. With this patch, we now respect dereference levels, etc. which should make us substantially more accurate. Proper handling of StratifiedAttrs will be done in a later patch. Patch by Jia Chen. Differential Revision: http://reviews.llvm.org/D21536 llvm-svn: 273596
* Refactor duplicated code. NFC.Rafael Espindola2016-06-231-20/+17
| | | | llvm-svn: 273595
* [X86] Extract HiPE prologue constants into metadataMichael Kuperstein2016-06-231-3/+31
| | | | | | | | | | | | | | | | | | | | | | X86FrameLowering::adjustForHiPEPrologue() contains a hard-coded offset into an Erlang Runtime System-internal data structure (the PCB). As the layout of this data structure is prone to change, this poses problems for maintaining compatibility. To address this problem, the compiler can produce this information as module-level named metadata. For example (where P_NSP_LIMIT is the offending offset): !hipe.literals = !{ !2, !3, !4 } !2 = !{ !"P_NSP_LIMIT", i32 152 } !3 = !{ !"X86_LEAF_WORDS", i32 24 } !4 = !{ !"AMD64_LEAF_WORDS", i32 24 } Patch by Magnus Lang Differential Revision: http://reviews.llvm.org/D20363 llvm-svn: 273593
* Fix the wasm build by including EndianStream.hReid Kleckner2016-06-231-0/+1
| | | | llvm-svn: 273591
* [IRCE] Use getTerminator instead of rbegin; NFCSanjoy Das2016-06-231-5/+5
| | | | llvm-svn: 273586
* Preserve DebugInfo when replacing values in DAGCombinerNirav Dave2016-06-236-18/+28
| | | | | | | | | | | | | | | | | | | | | Recommiting after correcting over-eager Debug Value transfer fixing PR28270. [DAG] Previously debug values would transfer debuginfo for the selected start node for a replacement which allows for debug to be dropped. Push debug value transfer to occur with node/value replacement in SelectionDAG, remove now extraneous transfers of debug values. This refixes PR9817 which was being incompletely checked in the testsuite. Reviewers: jyknight Subscribers: dblaikie, llvm-commits Differential Revision: http://reviews.llvm.org/D21037 llvm-svn: 273585
* [ValueTracking] simplify logic in ComputeNumSignBits (NFCI)Sanjay Patel2016-06-231-16/+9
| | | | | | | | | | | This was noted in http://reviews.llvm.org/D21610 . The previous code predated the use of APInt ( http://reviews.llvm.org/rL47654 ), so it had to account for the fixed width of uint64_t. Now that we're using the variable width APInt, we can remove some complexity. llvm-svn: 273584
* [ARM] Lower (select_cc k k (select_cc ~k ~k x)) into (SSAT l_k x)Pablo Barrio2016-06-234-1/+141
| | | | | | | | | | | | | | | | | Summary: SSAT saturates an integer, making sure that its value lies within an interval [-k, k]. Since the constant is given to SSAT as the number of bytes set to one, k + 1 must be a power of 2, otherwise the optimization is not possible. Also, the select_cc must use < and > respectively so that they define an interval. Reviewers: mcrosier, jmolloy, rengolin Subscribers: aemerson, rengolin, llvm-commits Differential Revision: http://reviews.llvm.org/D21372 llvm-svn: 273581
* [codeview] Emit retained typesHans Wennborg2016-06-232-0/+17
| | | | | | Differential Revision: http://reviews.llvm.org/D21630 llvm-svn: 273579
* Revert r273567 "[SystemZ] Let z13 also support FeatureMiscellaneousExtensions."Hans Wennborg2016-06-231-1/+0
| | | | | | It broke test/CodeGen/SystemZ/vec-extract-02.ll llvm-svn: 273575
* Revert r273568 "Remangle intrinsics names when types are renamed"Hans Wennborg2016-06-234-76/+2
| | | | | | It broke 2008-07-15-Bswap.ll and 2009-09-01-PostRAProlog.ll llvm-svn: 273574
* Remangle intrinsics names when types are renamedArtur Pilipenko2016-06-234-2/+76
| | | | | | | | | | | This is a fix for the problem mentioned in "LTO and intrinsics mangling" llvm-dev mail thread: http://lists.llvm.org/pipermail/llvm-dev/2016-April/098387.html Reviewers: mehdi_amini, reames Differential Revision: http://reviews.llvm.org/D19373 llvm-svn: 273568
* [SystemZ] Let z13 also support FeatureMiscellaneousExtensions.Jonas Paulsson2016-06-231-0/+1
| | | | | | | | | This processor feature had been left out by mistake from the z13 ProcessorModel. Reviewed by Ulrich Weigand. llvm-svn: 273567
* Explicitly specify the ANSI version of these Win32 APIs. While these are ↵Aaron Ballman2016-06-232-8/+8
| | | | | | seemingly unrelated changes, they are all NFC because we currently default to the ANSI versions of the APIs when building for Windows. This simply makes the ANSI usage explicit. llvm-svn: 273564
* [LoopUnrollAnalyzer] Fix a bug in UnrolledInstAnalyzer::visitLoad.Michael Zolotukhin2016-06-231-1/+1
| | | | | | | | | | | When simplifying a load we need to make sure that the type of the simplified value matches the type of the instruction we're processing. In theory, we can handle casts here as we deal with constant data, but since it's not implemented at the moment, we at least need to bail out. This fixes PR28262. llvm-svn: 273562
* [AMDGPU] Enable absolute expression initializer for amd_kernel_code_t fields.Valery Pykhtin2016-06-234-23/+26
| | | | | | Differential Revision: http://reviews.llvm.org/D21380 llvm-svn: 273561
* Allow DeadStoreElimination to track combinations of partial later wrtiesHal Finkel2016-06-231-2/+73
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | DeadStoreElimination can currently remove a small store rendered unnecessary by a later larger one, but could not remove a larger store rendered unnecessary by a series of later smaller ones. This adds that capability. It works by keeping a map, which is used as an effective interval map, for each store later overwritten only partially, and filling in that interval map as more such stores are discovered. No additional walking or aliasing queries are used. In the map forms an interval covering the the entire earlier store, then it is dead and can be removed. The map is used as an interval map by storing a mapping between the ending offset and the beginning offset of each interval. I discovered this problem when investigating a performance issue with code like this on PowerPC: #include <complex> using namespace std; complex<float> bar(complex<float> C); complex<float> foo(complex<float> C) { return bar(C)*C; } which produces this: define void @_Z4testSt7complexIfE(%"struct.std::complex"* noalias nocapture sret %agg.result, i64 %c.coerce) { entry: %ref.tmp = alloca i64, align 8 %tmpcast = bitcast i64* %ref.tmp to %"struct.std::complex"* %c.sroa.0.0.extract.shift = lshr i64 %c.coerce, 32 %c.sroa.0.0.extract.trunc = trunc i64 %c.sroa.0.0.extract.shift to i32 %0 = bitcast i32 %c.sroa.0.0.extract.trunc to float %c.sroa.2.0.extract.trunc = trunc i64 %c.coerce to i32 %1 = bitcast i32 %c.sroa.2.0.extract.trunc to float call void @_Z3barSt7complexIfE(%"struct.std::complex"* nonnull sret %tmpcast, i64 %c.coerce) %2 = bitcast %"struct.std::complex"* %agg.result to i64* %3 = load i64, i64* %ref.tmp, align 8 store i64 %3, i64* %2, align 4 ; <--- ***** THIS SHOULD NOT BE HERE **** %_M_value.realp.i.i = getelementptr inbounds %"struct.std::complex", %"struct.std::complex"* %agg.result, i64 0, i32 0, i32 0 %4 = lshr i64 %3, 32 %5 = trunc i64 %4 to i32 %6 = bitcast i32 %5 to float %_M_value.imagp.i.i = getelementptr inbounds %"struct.std::complex", %"struct.std::complex"* %agg.result, i64 0, i32 0, i32 1 %7 = trunc i64 %3 to i32 %8 = bitcast i32 %7 to float %mul_ad.i.i = fmul fast float %6, %1 %mul_bc.i.i = fmul fast float %8, %0 %mul_i.i.i = fadd fast float %mul_ad.i.i, %mul_bc.i.i %mul_ac.i.i = fmul fast float %6, %0 %mul_bd.i.i = fmul fast float %8, %1 %mul_r.i.i = fsub fast float %mul_ac.i.i, %mul_bd.i.i store float %mul_r.i.i, float* %_M_value.realp.i.i, align 4 store float %mul_i.i.i, float* %_M_value.imagp.i.i, align 4 ret void } the problem here is not just that the i64 store is unnecessary, but also that it blocks further backend optimizations of the other uses of that i64 value in the backend. In the future, we might want to add a special case for handling smaller accesses (e.g. using a bit vector) if the map mechanism turns out to be noticeably inefficient. A sorted vector is also a possible replacement for the map for small numbers of tracked intervals. Differential Revision: http://reviews.llvm.org/D18586 llvm-svn: 273559
* [mips] Don't derive the default ABI from the CPU in the backend.Daniel Sanders2016-06-231-28/+3
| | | | | | | | | | | | | | | | | | | | | | | | Summary: The backend has no reason to behave like a driver and should generally do as it's told (and error out if it can't) instead of trying to figure out what the API user meant. The default ABI is still derived from the arch component as a concession to backwards compatibility. API-users that previously passed an explicit CPU and a triple that was inconsistent with the CPU (e.g. mips-linux-gnu and mips64r2) may get a different ABI to what they got before. However, it's expected that there are no such users on the basis that CodeGen has been asserting that the triple is consistent with the selected ABI for several releases. API-users that were consistent or passed '' or 'generic' as the CPU will see no difference. Reviewers: sdardis, rafael Subscribers: rafael, dsanders, sdardis, llvm-commits Differential Revision: http://reviews.llvm.org/D21466 llvm-svn: 273557
* [ARM] Use member initializers in ARMSubtarget. NFCIDiana Picus2016-06-231-66/+22
| | | | | | | | | Move most of the initializations in ARMSubtarget::initializeEnvironment to member initializers. Change suggested by Matthias Braun (see http://reviews.llvm.org/D21432). llvm-svn: 273556
* [mips][ias] Integers are not registers.Daniel Sanders2016-06-231-6/+0
| | | | | | | | | | | | | | | | | | | Summary: When parseAnyRegister() encounters a symbol alias, it parses integers and adds a corresponding expression to the operand list. This is clearly wrong since the only operands that parseAnyRegister() should be accepting are registers. It's not clear why this code was added and there are no test cases that cover it. I think it might be leftover from when searchSymbolAlias() was more widely used. Reviewers: sdardis Subscribers: dsanders, sdardis, llvm-commits Differential Revision: http://reviews.llvm.org/D21377 llvm-svn: 273555
* [AMDGPU] Remove exit-on-error in test (PR27761)Diana Picus2016-06-232-2/+5
| | | | | | | | | | | | | | | | | The exit-on-error flag was necessary in order to avoid an assertion when handling DYNAMIC_STACKALLOC nodes in SelectionDAGLegalize. We can avoid the assertion by creating some dummy nodes. This enables us to remove the exit-on-error flag on the first 2 run lines (SI), but on the third run line (R600) we would run into another assertion when trying to reserve indirect registers. This patch also replaces that assertion with an early exit from the function. Fixes PR27761. Differential Revision: http://reviews.llvm.org/D20852 llvm-svn: 273550
* [mips] Fix dext/dins definitionsSimon Dardis2016-06-231-6/+8
| | | | | | | | | | | dext and dins, along with their 'm' and 'u' variants are defined in mips64r2, not mips64. Reviewers: dsanders, vkalintiris Differential Review: http://reviews.llvm.org/D21608 llvm-svn: 273549
* [IfConversion] Bugfix: Don't use undef flag while adding use operands.Jonas Paulsson2016-06-231-3/+16
| | | | | | | | | | | | | | | IfConversion used to always add the undef flag when adding a use operand on a newly predicated instruction. This would be an operand for the register being conditionally redefined. Due to the undef flag, the liveness of this register prior to the predicated instruction would get lost. This patch changes this so that such use operands are added only when the register is live, without the undef flag. Reviewed by Quentin Colombet. http://reviews.llvm.org/D209077 llvm-svn: 273545
* [ARM] Do not test for CPUs, use SubtargetFeatures (Part 1). NFCIDiana Picus2016-06-236-25/+91
| | | | | | | | | | | | | This is a cleanup commit similar to r271555, but for ARM. The end goal is to get rid of the isSwift / isCortexXY / isWhatever methods. Since the ARM backend seems to have quite a lot of calls to these methods, I intend to submit 5-6 subtarget features at a time, instead of one big lump. Differential Revision: http://reviews.llvm.org/D21432 llvm-svn: 273544
* [AVX512] Remove masked unpack intrinsics and autoupgrade to vectorshuffle ↵Craig Topper2016-06-233-72/+46
| | | | | | and selects. llvm-svn: 273543
* [X86] Add assert to ensure only 128-bit vector types are used. 256 or ↵Craig Topper2016-06-231-0/+2
| | | | | | 512-bit would require lane handling which is missing. llvm-svn: 273542
* Fix doubly included headerMatt Arsenault2016-06-231-1/+0
| | | | llvm-svn: 273528
* [libFuzzer] Add standard license info and comment header to AFLDriverTest.cppVitaly Buka2016-06-231-0/+4
| | | | | | | | | | | | Summary: Add license info and brief description of file to AFLDriverTest.cpp. Reviewers: kcc, aizatsky Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D21487 llvm-svn: 273527
* Use C++ comments for large block comment.Eric Christopher2016-06-231-16/+17
| | | | llvm-svn: 273526
* AMDGPU: readlane/writelane do not read execMatt Arsenault2016-06-232-2/+26
| | | | llvm-svn: 273525
* Fix unused variable warning by folding the temporary into the debug statement.Eric Christopher2016-06-231-2/+2
| | | | llvm-svn: 273523
* [SCCP] Don't assume all Constants are ConstantIntDavid Majnemer2016-06-231-8/+8
| | | | | | This fixes PR28269. llvm-svn: 273521
* [IRObjectFile] Try to be defensive, add a break.Davide Italiano2016-06-231-0/+1
| | | | | | Suggested by Sean Silva. llvm-svn: 273519
* Revert r273456, "Preserve DebugInfo when replacing values in DAGCombiner" as ↵Peter Collingbourne2016-06-236-22/+12
| | | | | | it caused pr28270. llvm-svn: 273518
* [codeview] Add EFLAGS to the list of CodeView register numbersReid Kleckner2016-06-221-1/+3
| | | | llvm-svn: 273516
* AMDGPU: Fix liveness when expanding m0 loopMatt Arsenault2016-06-222-23/+67
| | | | llvm-svn: 273514
* [RS4GC] Use StringRef; NFCSanjoy Das2016-06-221-4/+3
| | | | | | Spotted during random inspection. llvm-svn: 273512
* Fix instance of -Wdelete-incompleteReid Kleckner2016-06-221-0/+1
| | | | llvm-svn: 273508
* Prune some includes from headers and sink some inline functionsReid Kleckner2016-06-227-0/+32
| | | | | | | | MCSymbol.h shouldn't pull in MCAssembler.h, just MCFragment.h. MCLinkerOptimizationHint.h shouldn't need MCMachObjectWriter.h. The rest is fixing the fallout. llvm-svn: 273507
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