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authorCraig Topper <craig.topper@gmail.com>2016-06-23 07:37:26 +0000
committerCraig Topper <craig.topper@gmail.com>2016-06-23 07:37:26 +0000
commit8f8bd37dd34335965a7cff88cae7ee0da44a1b47 (patch)
tree831e47fff5c3bbb5e0b5673ee03d2045cb1d2517 /llvm/lib
parent47867200a2880ef18e9e4b55ac28cf4f37343569 (diff)
downloadbcm5719-llvm-8f8bd37dd34335965a7cff88cae7ee0da44a1b47.tar.gz
bcm5719-llvm-8f8bd37dd34335965a7cff88cae7ee0da44a1b47.zip
[X86] Add assert to ensure only 128-bit vector types are used. 256 or 512-bit would require lane handling which is missing.
llvm-svn: 273542
Diffstat (limited to 'llvm/lib')
-rw-r--r--llvm/lib/Target/X86/X86ISelLowering.cpp2
1 files changed, 2 insertions, 0 deletions
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp
index 11b98003f57..54e5536c36e 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -4684,6 +4684,7 @@ static SDValue getOnesVector(EVT VT, const X86Subtarget &Subtarget,
/// Returns a vector_shuffle node for an unpackl operation.
static SDValue getUnpackl(SelectionDAG &DAG, const SDLoc &dl, MVT VT,
SDValue V1, SDValue V2) {
+ assert(VT.is128BitVector() && "Expected a 128-bit vector type");
unsigned NumElems = VT.getVectorNumElements();
SmallVector<int, 8> Mask(NumElems);
for (unsigned i = 0, e = NumElems/2; i != e; ++i) {
@@ -4696,6 +4697,7 @@ static SDValue getUnpackl(SelectionDAG &DAG, const SDLoc &dl, MVT VT,
/// Returns a vector_shuffle node for an unpackh operation.
static SDValue getUnpackh(SelectionDAG &DAG, const SDLoc &dl, MVT VT,
SDValue V1, SDValue V2) {
+ assert(VT.is128BitVector() && "Expected a 128-bit vector type");
unsigned NumElems = VT.getVectorNumElements();
SmallVector<int, 8> Mask(NumElems);
for (unsigned i = 0, Half = NumElems/2; i != Half; ++i) {
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