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* Since extload can also be used by FP, split STDIntExtLoad into two parts,Nate Begeman2005-12-181-2/+5
| | | | | | | one for use with extload, one for use with sextload and zextload, which are integer only. llvm-svn: 24814
* Add constant pool support, including folding into addresses.Chris Lattner2005-12-183-2/+24
| | | | | | Pretty print addresses a bit, to not print [%r1+%g0]: just print [%r1] llvm-svn: 24813
* Teach the addressing mode stuff to fold "%lo" into 'ri' addressing modes,Chris Lattner2005-12-182-1/+20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | allowing us to compile this: to this: %G1 = external global int %G2 = external global int void %test() { %X = load int* %G1 store int %X, int* %G2 ret void } test: save -96, %sp, %sp sethi %hi(G1), %l0 ld [%l0+%lo(G1)], %l0 sethi %hi(G2), %l1 st %l0, [%l1+%lo(G2)] restore %g0, %g0, %g0 retl nop instead of this: test: save -96, %sp, %sp sethi %hi(G1), %l0 or %g0, %lo(G1), %l1 ld [%l1+%l0], %l0 sethi %hi(G2), %l1 or %g0, %lo(G2), %l2 st %l0, [%l2+%l1] restore %g0, %g0, %g0 retl nop llvm-svn: 24812
* Add initial support for global variables, and fix a bug in addr mode selectionChris Lattner2005-12-182-3/+21
| | | | | | where we didn't select the operands. llvm-svn: 24811
* Claiming that branch targets are registers is not very wholesome. Change themChris Lattner2005-12-181-51/+56
| | | | | | to be basic blocks. Also, add uncond branches. llvm-svn: 24810
* Add unordered comparisonsChris Lattner2005-12-181-13/+8
| | | | llvm-svn: 24809
* Add patterns to the rest of the int condbranches and some of the fp branchesChris Lattner2005-12-181-23/+46
| | | | llvm-svn: 24808
* Add initial conditional branch support. This doesn't actually work yet dueChris Lattner2005-12-184-46/+160
| | | | | | to a bug in the scheduler. llvm-svn: 24807
* Simplify codeChris Lattner2005-12-181-7/+2
| | | | llvm-svn: 24806
* Eliminate CMPri, which is a synonym for SUBCCriChris Lattner2005-12-172-8/+3
| | | | llvm-svn: 24805
* allow custom expansion of BR_CCChris Lattner2005-12-171-11/+25
| | | | llvm-svn: 24804
* add fneg,fabs,fsqrt instructionsChris Lattner2005-12-172-4/+16
| | | | llvm-svn: 24803
* Add patterns for fround/fextend and the funny fsmuld instructionChris Lattner2005-12-171-4/+8
| | | | llvm-svn: 24802
* Add FP +,-,*,/Chris Lattner2005-12-171-8/+16
| | | | llvm-svn: 24801
* Give patterns to F3_3 instructionsChris Lattner2005-12-172-21/+22
| | | | llvm-svn: 24800
* Implement 64-bit add/sub, make sure to receive and return 64-bit args withChris Lattner2005-12-171-4/+32
| | | | | | the right halves in the right regs llvm-svn: 24799
* implement div and remChris Lattner2005-12-171-0/+26
| | | | llvm-svn: 24798
* implement MULHU/MULHS for 64-bit multipliesChris Lattner2005-12-171-0/+11
| | | | llvm-svn: 24797
* Add patterns for multiply, simplify Y register handling stuff, add RDY ↵Chris Lattner2005-12-173-17/+17
| | | | | | instruction llvm-svn: 24796
* Make the addressing modes smarterChris Lattner2005-12-172-10/+21
| | | | llvm-svn: 24795
* remove some unused instructionsChris Lattner2005-12-171-81/+6
| | | | llvm-svn: 24794
* add andn/orn/xorn patterns. This allows us to compile this:Chris Lattner2005-12-171-3/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | long %test(ubyte, short, long %X, long %Y) { %A = xor long %X, -1 %B = and long %Y, %A ret long %B } to this: test: save -96, %sp, %sp andn %i4, %i2, %i0 andn %i5, %i3, %i1 restore %g0, %g0, %g0 retl nop instead of this: test: save -96, %sp, %sp xor %i2, -1, %l0 xor %i3, -1, %l1 and %i4, %l0, %i0 and %i5, %l1, %i1 restore %g0, %g0, %g0 retl nop The simpleisel emits: :( test: save -96, %sp, %sp or %g0, -1, %l0 or %g0, -1, %l0 or %g0, -1, %l0 or %g0, -1, %l1 xor %i2, %l0, %l0 xor %i3, %l1, %l1 and %i4, %l0, %i0 and %i5, %l1, %i1 restore %g0, %g0, %g0 retl nop llvm-svn: 24793
* Add support for 64-bit argumentsChris Lattner2005-12-171-0/+12
| | | | llvm-svn: 24792
* Sparc doesn't have sext_inregChris Lattner2005-12-171-0/+5
| | | | llvm-svn: 24791
* add patterns for FP storesChris Lattner2005-12-171-20/+12
| | | | llvm-svn: 24790
* Add [reg+reg] integer storesChris Lattner2005-12-171-0/+15
| | | | llvm-svn: 24789
* Add store patternsChris Lattner2005-12-171-3/+6
| | | | llvm-svn: 24788
* add truncstoreChris Lattner2005-12-171-3/+9
| | | | llvm-svn: 24787
* add fp load patterns, switch rest of loads and stores to use addrmodesChris Lattner2005-12-171-30/+28
| | | | llvm-svn: 24786
* Add integer load[r+r] forms.Chris Lattner2005-12-171-0/+23
| | | | llvm-svn: 24785
* Rename load/store instructions to include an RI suffixChris Lattner2005-12-172-54/+51
| | | | llvm-svn: 24784
* Add patterns for the rest of the loads. Add 'ri' suffixes to the load and ↵Chris Lattner2005-12-171-31/+35
| | | | | | store insts llvm-svn: 24783
* Add basic addressing mode support and one load.Chris Lattner2005-12-173-3/+48
| | | | llvm-svn: 24782
* eliminate some redundancyChris Lattner2005-12-171-8/+8
| | | | llvm-svn: 24781
* Use a combination of sethi and or to build arbitrary immediates.Chris Lattner2005-12-171-0/+7
| | | | llvm-svn: 24780
* Use sethi to build large immediates with zeros at the bottomChris Lattner2005-12-172-3/+14
| | | | llvm-svn: 24779
* Add shift and small immediate supportChris Lattner2005-12-171-6/+20
| | | | llvm-svn: 24778
* Add some basic reg-reg instructionsChris Lattner2005-12-171-5/+10
| | | | llvm-svn: 24777
* Add empty patterns to all F3_1 instructionsChris Lattner2005-12-172-43/+45
| | | | llvm-svn: 24776
* Darwin API issue: indirect load of external and weak symbols.Evan Cheng2005-12-171-3/+8
| | | | llvm-svn: 24775
* Add some simple integer patterns. This allows us to compile this:Chris Lattner2005-12-171-5/+19
| | | | | | | | | | | | | | | | | | | | | | int %test(int %A) { %B = add int %A, 1 %C = xor int %B, 123 ret int %C } into this: test: save -96, %sp, %sp add %i0, 1, %l0 xor %l0, 123, %i0 restore %g0, %g0, %g0 retl nop for example. I guess it would make sense to add reg/reg versions too. llvm-svn: 24774
* Implement ret with operand, giving us this:Chris Lattner2005-12-171-2/+33
| | | | | | | | int %test(int %A) { ret int %A } llvm-svn: 24773
* Add a pattern for 'ret'. This now compiles:Chris Lattner2005-12-171-1/+1
| | | | | | | | void %test() { ret void } :) llvm-svn: 24772
* Add empty patterns for F3_2 instructionsChris Lattner2005-12-172-56/+58
| | | | llvm-svn: 24771
* Implement LowerArguments, at least for the first 6 integer argsChris Lattner2005-12-171-2/+63
| | | | llvm-svn: 24770
* Add the framework for a dag-dag iselChris Lattner2005-12-174-2/+185
| | | | llvm-svn: 24769
* Remove a few lines of dead code.Evan Cheng2005-12-171-3/+0
| | | | llvm-svn: 24768
* asmprinter done, added crucial missing stepChris Lattner2005-12-171-3/+2
| | | | llvm-svn: 24767
* Use the AsmPrinter for global variable init printing. This eliminates aChris Lattner2005-12-171-209/+2
| | | | | | | bunch of code and causes V8 to start using the fancy .asciz directive that the sun assembler supports. llvm-svn: 24766
* Switch constant pool printing over to use the Shared AsmPrinter versionChris Lattner2005-12-171-27/+10
| | | | llvm-svn: 24765
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