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* make the asm matcher emitter reject instructions that have commentsChris Lattner2010-11-011-2/+2
| | | | | | | in their asmstring. Fix the two x86 "NOREX" instructions that have them. If these comments are important, the instlowering stuff can print them. llvm-svn: 117897
* reject instructions that contain a \n in their asmstring. MarkChris Lattner2010-11-012-8/+13
| | | | | | | various X86 and ARM instructions that are bitten by this as isCodeGenOnly, as they are. llvm-svn: 117884
* Revert r117876 for now, it's causing more testsuite failures.Eric Christopher2010-10-311-2/+0
| | | | llvm-svn: 117879
* Disable the peephole optimizer until 186.crafty on armv6 is fixed. This is whatBill Wendling2010-10-311-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | looks like is happening: Without the peephole optimizer: (1) sub r6, r6, #32 orr r12, r12, lr, lsl r9 orr r2, r2, r3, lsl r10 (x) cmp r6, #0 ldr r9, LCPI2_10 ldr r10, LCPI2_11 (2) sub r8, r8, #32 (a) movge r12, lr, lsr r6 (y) cmp r8, #0 LPC2_10: ldr lr, [pc, r10] (b) movge r2, r3, lsr r8 With the peephole optimizer: ldr r9, LCPI2_10 ldr r10, LCPI2_11 (1*) subs r6, r6, #32 (2*) subs r8, r8, #32 (a*) movge r12, lr, lsr r6 (b*) movge r2, r3, lsr r8 (1) is used by (x) for the conditional move at (a). (2) is used by (y) for the conditional move at (b). After the peephole optimizer, these the flags resulting from (1*) are ignored and only the flags from (2*) are considered for both conditional moves. llvm-svn: 117876
* Attach a GCModuleInfo to a MachineFunction.Nicolas Geoffray2010-10-312-3/+6
| | | | llvm-svn: 117867
* fix the !eq operator in tblgen to return a bit instead of an int.Chris Lattner2010-10-312-0/+6
| | | | | | | | Use this to make the X86 and ARM targets set isCodeGenOnly=1 automatically for their instructions that have Format=Pseudo, resolving a hack in tblgen. llvm-svn: 117862
* two changes: make the asmmatcher generator ignore ARM pseudos properly,Chris Lattner2010-10-314-9/+19
| | | | | | | and make it a hard error for instructions to not have an asm string. These instructions should be marked isCodeGenOnly. llvm-svn: 117861
* reapply r117858 with apparent editor malfunction fixed (somehow I Chris Lattner2010-10-315-11/+21
| | | | | | got a dulicated line). llvm-svn: 117860
* revert r117858 while I check out a failure I missed.Chris Lattner2010-10-315-21/+11
| | | | llvm-svn: 117859
* the asm matcher can't handle operands with modifiers (like ${foo:bar}).Chris Lattner2010-10-315-11/+21
| | | | | | | | | | | Instead of silently ignoring these instructions, emit a hard error and force the target author to either refactor the target or mark the instruction 'isCodeGenOnly'. Mark a few instructions in ARM and MBlaze as isCodeGenOnly the are doing this. llvm-svn: 117858
* sketch out the planned instruction alias mechanism, add some comments aboutChris Lattner2010-10-311-0/+14
| | | | | | how the push/pop mnemonic aliases are wrong. llvm-svn: 117857
* Factorize the duplicated logic for choosing the right argumentDuncan Sands2010-10-314-56/+36
| | | | | | | calling convention out of the fast and normal ISel files, and into the calling convention TD file. llvm-svn: 117856
* Remove CCAssignFnForRet from X86 FastISel in favour of RetCC_X86,Duncan Sands2010-10-311-16/+1
| | | | | | | which has the same logic specified in the CallingConv TD file. This brings FastISel in line with the standard X86 ISel. llvm-svn: 117855
* Add support for files with more than 65280 sections. No testcase sinceRafael Espindola2010-10-311-42/+109
| | | | | | it would be a bit too big :-) llvm-svn: 117849
* Make sure we have a legal type (and simple) before continuing.Eric Christopher2010-10-301-1/+4
| | | | llvm-svn: 117848
* Resolve a terrible hack in tblgen: instead of hardcodingChris Lattner2010-10-301-2/+2
| | | | | | | "In32BitMode" and "In64BitMode" into tblgen, allow any predicate that inherits from AssemblerPredicate. llvm-svn: 117831
* Implement (and document!) support for MnemonicAlias's to have Requires Chris Lattner2010-10-302-14/+20
| | | | | | | | | | | directives, allowing things like this: def : MnemonicAlias<"pop", "popl">, Requires<[In32BitMode]>; def : MnemonicAlias<"pop", "popq">, Requires<[In64BitMode]>; Move the rest of the X86 MnemonicAliases over to the .td file. llvm-svn: 117830
* really zap alias.Chris Lattner2010-10-301-1/+0
| | | | llvm-svn: 117824
* move fcompi alias to .td file and zap some useless code.Chris Lattner2010-10-302-11/+1
| | | | llvm-svn: 117823
* move rep aliases to td fileChris Lattner2010-10-302-5/+7
| | | | llvm-svn: 117822
* move sal aliases to .td file.Chris Lattner2010-10-302-5/+5
| | | | llvm-svn: 117821
* fix an encoding mismatch where "sal %eax, 1" was not using the short encodingChris Lattner2010-10-301-1/+1
| | | | | | for shl. Caught by inspection. llvm-svn: 117820
* move a bunch more aliases from .cpp -> .td file.Chris Lattner2010-10-302-22/+27
| | | | llvm-svn: 117819
* move cmov aliases to .td file.Chris Lattner2010-10-302-49/+25
| | | | llvm-svn: 117818
* move setcc and jcc aliases from .cpp to .tdChris Lattner2010-10-302-14/+28
| | | | llvm-svn: 117817
* move some code.Chris Lattner2010-10-301-33/+35
| | | | llvm-svn: 117816
* implement (and document!) the first kind of MC assembler alias, which Chris Lattner2010-10-302-15/+23
| | | | | | | just remaps one mnemonic to another. Convert a few of the X86 aliases from .cpp to .td code. llvm-svn: 117815
* Now that the MallocInst no longer exists, this workaround forDuncan Sands2010-10-301-5/+0
| | | | | | it claiming not to have side-effects is no longer needed. llvm-svn: 117789
* Add FIXME.Jim Grosbach2010-10-301-0/+2
| | | | llvm-svn: 117787
* Clean up comments.Jim Grosbach2010-10-301-1/+5
| | | | llvm-svn: 117785
* If a function does a volatile load from a global constant, do notDuncan Sands2010-10-301-4/+4
| | | | | | | | | consider it to be readonly. In fact, don't even consider it to be readonly if it does a volatile load from an AllocaInst either (it is debatable as to whether readonly would be correct or not in this case; play safe for the moment). This fixes PR8279. llvm-svn: 117783
* Tidy up.Jim Grosbach2010-10-301-1/+1
| | | | llvm-svn: 117782
* stay out of the reserved namespaceChris Lattner2010-10-301-6/+6
| | | | llvm-svn: 117773
* simplify this code.Chris Lattner2010-10-301-8/+4
| | | | llvm-svn: 117771
* split MaybeParseRegister into its two logical uses, eliminating malloc+free ↵Chris Lattner2010-10-301-35/+38
| | | | | | traffic. llvm-svn: 117769
* Avoid re-evaluating MI.getNumOperands() every iteration of the loop.Jim Grosbach2010-10-301-1/+1
| | | | llvm-svn: 117766
* Include MachineBasicBlock numbers in viewCFG() output.Jakob Stoklund Olesen2010-10-301-8/+6
| | | | llvm-svn: 117765
* Make sure copies are inserted after any exception handling labels at the top ofJakob Stoklund Olesen2010-10-301-1/+1
| | | | | | a basic block. llvm-svn: 117764
* Add SkipPHIsAndLabels from PHIElimination to MachineBasicBlock. It is neededJakob Stoklund Olesen2010-10-301-0/+7
| | | | | | elsewhere. llvm-svn: 117763
* Disable more of physical register live intervals verification.Jakob Stoklund Olesen2010-10-301-2/+3
| | | | llvm-svn: 117762
* Print out register class of spilled register.Jakob Stoklund Olesen2010-10-301-2/+4
| | | | llvm-svn: 117761
* Overhaul memory barriers in the ARM backend. Radar 8601999.Bob Wilson2010-10-305-131/+61
| | | | | | | | | | | | | | | | | | | There were a number of issues to fix up here: * The "device" argument of the llvm.memory.barrier intrinsic should be used to distinguish the "Full System" domain from the "Inner Shareable" domain. It has nothing to do with using DMB vs. DSB instructions. * The compiler should never need to emit DSB instructions. Remove the ARMISD::SYNCBARRIER node and also remove the instruction patterns for DSB. * Merge the separate DMB/DSB instructions for options only used for the disassembler with the default DMB/DSB instructions. Add the default "full system" option ARM_MB::SY to the ARM_MB::MemBOpt enum. * Add a separate ARMISD::MEMBARRIER_MCR node for subtargets that implement a data memory barrier using the MCR instruction. * Fix up encodings for these instructions (except MCR). I also updated the tests and added a few new ones to check for DMB options that were not currently being exercised. llvm-svn: 117756
* Encode the register list operands for ARM mode LDM/STM instructions.Jim Grosbach2010-10-304-0/+23
| | | | llvm-svn: 117753
* Some instructions end with an "ls" prefix, but it doesn't indicate that they areBill Wendling2010-10-291-3/+9
| | | | | | conditional. Check for those instructions explicitly. llvm-svn: 117747
* Teach machine cse to eliminate instructions with multiple physreg uses and ↵Evan Cheng2010-10-291-50/+45
| | | | | | defs. rdar://8610857. llvm-svn: 117745
* Remove hard tab characters.Jim Grosbach2010-10-291-3/+3
| | | | llvm-svn: 117742
* 80 column fix.Jim Grosbach2010-10-291-2/+2
| | | | llvm-svn: 117741
* trailing whitespaceJim Grosbach2010-10-291-2/+2
| | | | llvm-svn: 117740
* s/getNEONVcvtImm32/getNEONVcvtImm32OpValue/ to be consistent with other operandJim Grosbach2010-10-293-3/+3
| | | | | | encoder functions. llvm-svn: 117738
* Fix fpscr <-> GPR latency info.Evan Cheng2010-10-293-4/+12
| | | | llvm-svn: 117737
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