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* Bug 18228 - Fix accepting bitcasts between vectors of pointers with aMatt Arsenault2014-01-221-16/+41
| | | | | | | | | | | | | different number of elements. Bitcasts were passing with vectors of pointers with different number of elements since the number of elements was checking SrcTy->getVectorNumElements() == SrcTy->getVectorNumElements() which isn't helpful. The addrspacecast was also wrong, but that case at least is caught by the verifier. Refactor bitcast and addrspacecast handling in castIsValid to be more readable and fix this problem. llvm-svn: 199821
* Fix inline assembly that switches between ARM and Thumb modesGreg Fitzgerald2014-01-223-9/+32
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch restores the ARM mode if the user's inline assembly does not. In the object streamer, it ensures that instructions following the inline assembly are encoded correctly and that correct mapping symbols are emitted. For the asm streamer, it emits a .arm or .thumb directive. This patch does not ensure that the inline assembly contains the ADR instruction to switch modes at runtime. The problem we need to solve is code like this: int foo(int a, int b) { int r = a + b; asm volatile( ".align 2 \n" ".arm \n" "add r0,r0,r0 \n" : : "r"(r)); return r+1; } If we compile this function in thumb mode then the inline assembly will switch to arm mode. We need to make sure that we switch back to thumb mode after emitting the inline assembly or we will incorrectly encode the instructions that follow (i.e. the assembly instructions for return r+1). Based on patch by David Peixotto Change-Id: Ib57f6d2d78a22afad5de8693fba6230ff56ba48b llvm-svn: 199818
* Remove param doxygen comment for non-existing parameter.Benjamin Kramer2014-01-221-1/+0
| | | | | | Found by -Wdocumentation. llvm-svn: 199814
* Pass the computed magic to createBinary and createObjectFile if available.Rafael Espindola2014-01-222-12/+14
| | | | | | | identify_magic is not free, so we should avoid calling it twice. The argument also makes it cheap for createBinary to just forward to createObjectFile. llvm-svn: 199813
* [x86] Silence unused diReg variable warning in non-asserting buildsDavid Woodhouse2014-01-221-4/+3
| | | | llvm-svn: 199812
* [x86] Fix uninitialized variable warning in translate{Src,Dst}IndexDavid Woodhouse2014-01-221-2/+6
| | | | llvm-svn: 199811
* [x86] Remove now-unused isSrcOp() and isDstOp() from X86AsmParserDavid Woodhouse2014-01-221-30/+0
| | | | llvm-svn: 199810
* [x86] Allow segment and address-size overrides for INS[BWLQ] (PR9385)David Woodhouse2014-01-222-13/+17
| | | | llvm-svn: 199809
* [x86] Allow segment and address-size overrides for OUTS[BWLQ] (PR9385)David Woodhouse2014-01-222-13/+16
| | | | llvm-svn: 199808
* [x86] Allow segment and address-size overrides for MOVS[BWLQ] (PR9385)David Woodhouse2014-01-222-21/+34
| | | | llvm-svn: 199807
* ]x86] Allow segment and address-size overrides for CMPS[BWLQ] (PR9385)David Woodhouse2014-01-225-5/+80
| | | | llvm-svn: 199806
* [x86] Allow address-size overrides for SCAS{8,16,32,64} (PR9385)David Woodhouse2014-01-222-5/+28
| | | | llvm-svn: 199805
* [x86] Allow address-size overrides for STOS[BWLQ] (PR9385)David Woodhouse2014-01-2212-35/+189
| | | | llvm-svn: 199804
* [x86] Allow segment and address-size overrides for LODS[BWLQ] (PR9385)David Woodhouse2014-01-2212-35/+212
| | | | llvm-svn: 199803
* Loop strength reduce: fix function name.Tim Northover2014-01-221-8/+8
| | | | llvm-svn: 199801
* AVX512: combining setcc and zext is wrong on AVX512Elena Demikhovsky2014-01-221-1/+4
| | | | | | because vector compare instruction puts result in mask register. llvm-svn: 199798
* MachineCopyPropagation has special logic for removing COPY instructions. It ↵James Molloy2014-01-221-8/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | will remove plain COPYs using eraseFromParent(), but if the COPY has imp-defs/imp-uses it will convert it to a KILL, to keep the imp-def around. This actually totally breaks and causes the machine verifier to cry in several cases, one of which being: %RAX<def> = COPY %RCX<kill> %ECX<def> = COPY %EAX<kill>, %RAX<imp-use,kill> These subregister copies are together identified as noops, so are both removed. However, the second one as it has an imp-use gets converted into a kill: %ECX<def> = KILL %EAX<kill>, %RAX<imp-use,kill> As the original COPY has been removed, the verifier goes into tears at the use of undefined EAX and RAX. There are several hacky solutions to this hacky problem (which is all to do with imp-use/def weirdnesses), but the least hacky I've come up with is to *always* remove COPYs by converting to KILLs. KILLs are no-ops to the code generator so the generated code doesn't change (which is why they were partially used in the first place), but using them also keeps the def/use and imp-def/imp-use chains alive: %RAX<def> = KILL %RCX<kill> %ECX<def> = KILL %EAX<kill>, %RAX<imp-use,kill> The patch passes all test cases including the ones that check the removal of MOVs in this circumstance, along with an extra test I added to check subregister behaviour (which made the machine verifier fall over before my patch). The patch also adds some DEBUG() statements because the file hadn't got any. llvm-svn: 199797
* [AArch64 NEON] Try to generate CONCAT_VECTOR when lowering BUILD_VECTOR or ↵Kevin Qin2014-01-222-29/+90
| | | | | | SHUFFLE_VECTOR. llvm-svn: 199791
* Reformat a loop for basic hygeine. Self review.Andrew Trick2014-01-221-5/+5
| | | | llvm-svn: 199788
* [Sparc] Add support for inline assembly constraints which specify registers ↵Venkatraman Govindaraju2014-01-221-0/+20
| | | | | | by their aliases. llvm-svn: 199786
* Fix typoMatt Arsenault2014-01-221-1/+1
| | | | llvm-svn: 199784
* [Sparc] Add support for inline assembly constraint 'I'. Venkatraman Govindaraju2014-01-222-0/+67
| | | | llvm-svn: 199781
* Change createObjectFile to return an ErrorOr.Rafael Espindola2014-01-224-18/+17
| | | | llvm-svn: 199776
* [Sparc] Do not add PC to _GLOBAL_OFFSET_TABLE_ address to access GOT in ↵Venkatraman Govindaraju2014-01-221-30/+94
| | | | | | | | absolute code. Fixes PR#18521 llvm-svn: 199775
* [SROA] Fix a bug which could cause the common type finding to returnChandler Carruth2014-01-211-22/+19
| | | | | | | | | | | | | inconsistent results for different orderings of alloca slices. The fundamental issue is that it is just always a mistake to return early from this function. There is no effective early exit to leverage. This patch stops trynig to do so and simplifies the code a bit as a consequence. Original diagnosis and patch by James Molloy with some name tweaks by me in part reflecting feedback from Duncan Smith on the mailing list. llvm-svn: 199771
* Be a bit more consistent about using ErrorOr when constructing Binary objects.Rafael Espindola2014-01-217-75/+74
| | | | | | | | | | | | | | | | | | | | | | | The constructors of classes deriving from Binary normally take an error_code as an argument to the constructor. My original intent was to change them to have a trivial constructor and move the initial parsing logic to a static method returning an ErrorOr. I changed my mind because: * A constructor with an error_code out parameter is extremely convenient from the implementation side. We can incrementally construct the object and give up when we find an error. * It is very efficient when constructing on the stack or when there is no error. The only inefficient case is where heap allocating and an error is found (we have to free the memory). The result is that this is a much smaller patch. It just standardizes the create* helpers to return an ErrorOr. Almost no functionality change: The only difference is that this found that we were trying to read past the end of COFF import library but ignoring the error. llvm-svn: 199770
* CodeGen: Stop treating vectors as aggregatesDuncan P. N. Exon Smith2014-01-211-1/+1
| | | | | | | | | Fix a crash in SjLjEHPrepare::lowerIncomingArguments caused by treating VectorType like an aggregate. It's first-class! <rdar://problem/15854596> llvm-svn: 199768
* Fix PR18572 - llc crash during GenericScheduler::initPolicy().Andrew Trick2014-01-211-4/+10
| | | | | | | Generalized the heuristic that looks at the (very rough) size of the register file before enabling regpressure tracking. llvm-svn: 199766
* Fix pointer info on PPC byval storesHal Finkel2014-01-211-6/+5
| | | | | | | | | | | For PPC64 SVR (and Darwin), the stores that take byval aggregate parameters from registers into the stack frame had MachinePointerInfo objects with incorrect offsets. These offsets are relative to the object itself, not to the stack frame base. This fixes self hosting on PPC64 when compiling with -enable-aa-sched-mi. llvm-svn: 199763
* Adding new LTO APIs to parse metadata nodes and extract linker options andYunzhong Gao2014-01-212-0/+47
| | | | | | | | dependent libraries from a bitcode module. Differential Revision: http://llvm-reviews.chandlerc.com/D2343 llvm-svn: 199759
* Rename these methods to match the style guide.Rafael Espindola2014-01-212-16/+16
| | | | llvm-svn: 199751
* [mips][sched] Split IILoad into II_L[BHWD], II_L[BHW]U, II_L[WD][LR], and ↵Daniel Sanders2014-01-215-31/+52
| | | | | | | | II_RESTORE No functional change since the InstrItinData's have been duplicated. llvm-svn: 199749
* [mips][sched] Split IIFmoveC1 into II_M[FT]C1, II_M[FT]HC1, II_DM[FT]C1Daniel Sanders2014-01-213-12/+22
| | | | | | No functional change since the InstrItinData's have been duplicated. llvm-svn: 199748
* [mips][sched] Split IIFStore into II_S[WD]C1, and II_S[WDU]XC1Daniel Sanders2014-01-213-14/+22
| | | | | | No functional change since the InstrItinData's have been duplicated. llvm-svn: 199747
* [NVPTX] Add missing patterns for div.approx with immediate denominatorJustin Holewinski2014-01-211-0/+12
| | | | llvm-svn: 199746
* [mips][sched] Split IIFLoad into II_L[WD]C1, and II_L[WDU]XC1Daniel Sanders2014-01-213-16/+23
| | | | | | No functional change since the InstrItinData's have been duplicated. llvm-svn: 199743
* [mips][sched] Removed IIFrecipFsqrtStep. No instructions use it.Daniel Sanders2014-01-211-2/+0
| | | | llvm-svn: 199742
* [mips][sched] Renamed II_FsqrtSingle and II_FsqrtDouble to II_SQRT_S and ↵Daniel Sanders2014-01-213-10/+10
| | | | | | | | II_SQRT_D respectively No functional change llvm-svn: 199741
* [mips][sched] Renamed II_FdivSingle and II_FdivDouble to II_DIV_S and ↵Daniel Sanders2014-01-213-8/+8
| | | | | | | | II_DIV_D respectively No functional change llvm-svn: 199738
* [mips][sched] Split IIFmulDouble into II_MUL_D, II_MADD_D, II_MSUB_D, ↵Daniel Sanders2014-01-213-18/+26
| | | | | | | | II_NMADD_D, and II_NMSUB_S No functional change since the InstrItinData's have been duplicated. llvm-svn: 199737
* [mips][sched] Split IIFmulSingle into II_MUL_S, II_MADD_S, II_MSUB_S, ↵Daniel Sanders2014-01-213-12/+20
| | | | | | | | II_NMADD_S, and II_NMSUB_S No functional change since the InstrItinData's have been duplicated. llvm-svn: 199734
* [mips][sched] Split IIFadd into II_ADD_[DS], II_SUB_[DS]Daniel Sanders2014-01-213-10/+16
| | | | | | No functional change since the InstrItinData's have been duplicated. llvm-svn: 199732
* [mips][sched] Split IIFcmp into II_C_CC_[SD]Daniel Sanders2014-01-213-32/+37
| | | | | | No functional change since the InstrItinData's have been duplicated. llvm-svn: 199728
* [mips][sched] Split IIFmove into II_C[FT]C1, II_MOV[FNTZ]_[SD], II_MOV_[SD]Daniel Sanders2014-01-214-43/+65
| | | | | | No functional change since the InstrItinData's have been duplicated. llvm-svn: 199727
* [mips][sched] Split IIFcvt into II_(ROUND|TRUNC|CEIL|FLOOR|CVT), II_ABS, II_NEGDaniel Sanders2014-01-213-63/+75
| | | | | | No functional change since the InstrItinData's have been duplicated. llvm-svn: 199722
* [mips][sched] Split IIslt into II_SLT_SLTU, II_SLTI_SLTIUDaniel Sanders2014-01-212-3/+4
| | | | | | No functional change since the InstrItinData's have been duplicated. llvm-svn: 199719
* Checked return warning from coverityRenato Golin2014-01-211-2/+3
| | | | llvm-svn: 199716
* ARM IAS: add support for .unwind_raw directiveSaleem Abdulrasool2014-01-213-0/+116
| | | | | | | | | | | | This implements the unwind_raw directive for the ARM IAS. The unwind_raw directive takes the form of a stack offset value followed by one or more bytes representing the opcodes to be emitted. The opcode emitted will interpreted as if it were assembled by the opcode assembler via the standard unwinding directives. Thanks to Logan Chien for an extra test! llvm-svn: 199707
* ARM IAS: support .personalityindexSaleem Abdulrasool2014-01-213-7/+109
| | | | | | | | | | | | | The .personalityindex directive is equivalent to the .personality directive with the ARM EABI personality with the specific index (0, 1, 2). Both of these directives indicate personality routines, so enhance the personality directive handling to take into account personalityindex. Bonus fix: flush the UnwindContext at the beginning of a new function. Thanks to Logan Chien for additional tests! llvm-svn: 199706
* [AArch64 NEON] Fix a bug caused by undef lane when generating VEXT.Kevin Qin2014-01-211-15/+21
| | | | | | | | It was commited as r199628 but reverted in r199628 as causing regression test failed. It's because of old vervsion of patch I used to commit. Sorry for mistake. llvm-svn: 199704
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