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| author | David Woodhouse <dwmw2@infradead.org> | 2014-01-22 15:31:32 +0000 |
|---|---|---|
| committer | David Woodhouse <dwmw2@infradead.org> | 2014-01-22 15:31:32 +0000 |
| commit | 7a7c192e3e896dc5160bdee536ece542fc3c3fc3 (patch) | |
| tree | f60579c6972216d1c33566df175f82881fdf47c0 /llvm/lib | |
| parent | fee418c2c0e6645045cb531aeabefdfa9b3f3ac3 (diff) | |
| download | bcm5719-llvm-7a7c192e3e896dc5160bdee536ece542fc3c3fc3.tar.gz bcm5719-llvm-7a7c192e3e896dc5160bdee536ece542fc3c3fc3.zip | |
[x86] Silence unused diReg variable warning in non-asserting builds
llvm-svn: 199812
Diffstat (limited to 'llvm/lib')
| -rw-r--r-- | llvm/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp | 7 |
1 files changed, 3 insertions, 4 deletions
diff --git a/llvm/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp b/llvm/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp index e8c9107f662..0e18a4e9f65 100644 --- a/llvm/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp +++ b/llvm/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp @@ -1318,11 +1318,10 @@ EncodeInstruction(const MCInst &MI, raw_ostream &OS, case X86II::Pseudo: llvm_unreachable("Pseudo instruction shouldn't be emitted"); case X86II::RawFrmDstSrc: { - unsigned diReg = MI.getOperand(0).getReg(); unsigned siReg = MI.getOperand(1).getReg(); - assert(((siReg == X86::SI && diReg == X86::DI) || - (siReg == X86::ESI && diReg == X86::EDI) || - (siReg == X86::RSI && diReg == X86::RDI)) && + assert(((siReg == X86::SI && MI.getOperand(0).getReg() == X86::DI) || + (siReg == X86::ESI && MI.getOperand(0).getReg() == X86::EDI) || + (siReg == X86::RSI && MI.getOperand(0).getReg() == X86::RDI)) && "SI and DI register sizes do not match"); // Emit segment override opcode prefix as needed (not for %ds). if (MI.getOperand(2).getReg() != X86::DS) |
