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* [X86] Move a setOperation action for ISD::TRUNCATE near another one in the ↵Craig Topper2017-09-281-2/+1
| | | | | | same if. Remove one that is redundant with another subtarget features. llvm-svn: 314446
* llvm-dwarfdump: implement --find for .apple_namesAdrian Prantl2017-09-284-11/+95
| | | | | | | | | | | | This patch implements the dwarfdump option --find=<name>. This option looks for a DIE in the accelerator tables and dumps it if found. This initial patch only adds support for .apple_names to keep the review small, adding the other sections and pubnames support should be trivial though. Differential Revision: https://reviews.llvm.org/D38282 llvm-svn: 314439
* [ORC] Fix the type of RTDyldObjectLinkingLayer::NotifyLoadedFtor.Lang Hames2017-09-281-1/+1
| | | | | | Bug found by Stefan Granitz. Thanks Stefan! llvm-svn: 314436
* [JumpThreading] Preserve DT and LVI across the passEvandro Menezes2017-09-283-65/+253
| | | | | | | | | | | | | | | | | JumpThreading now preserves dominance and lazy value information across the entire pass. The pass manager is also informed of this preservation with the goal of DT and LVI being recalculated fewer times overall during compilation. This change prepares JumpThreading for enhanced opportunities; particularly those across loop boundaries. Patch by: Brian Rzycki <b.rzycki@samsung.com>, Sebastian Pop <s.pop@samsung.com> Differential revision: https://reviews.llvm.org/D37528 llvm-svn: 314435
* [X86] Use BWI instructions to improve lowering of v32i8 MULHU/SCraig Topper2017-09-281-0/+18
| | | | | | | | | | | | | | Summary: If we have BWI instructions we can widen to v32i16 to do the multiply instead of splitting. Reviewers: RKSimon, spatel, zvi Reviewed By: zvi Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D38305 llvm-svn: 314432
* [X86] Remove dead code from X86ISelDAGToDAG.cpp multiply handlingCraig Topper2017-09-281-1/+1
| | | | | | | | | | | | | | | | | Summary: Lowering never creates X86ISD::UMUL for 8-bit types. X86ISD::UMUL8 is used instead. If X86ISD::UMUL 8-bit were ever used it would crash. DAGCombiner replaces UMUL_LOHI/SMUL_LOHI with a wider MUL and a shift if the type twice as wide is legal. So we should never see i8 UMUL_LOHI/SMUL_LOHI. In fact I think there was a bug in part of the i8 code. Similar is true for i16 though without the bug. Reviewers: RKSimon, spatel, zvi Reviewed By: zvi Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D38276 llvm-svn: 314430
* [X86] Use correct subvector index when combining two insert subvectors ↵Craig Topper2017-09-281-1/+1
| | | | | | | | | | featuring zero vectors. Previously we were using one of the subvector indices twice. The included test case causes an assert without this change. Thanks to Simon Pilgrim for catching this. llvm-svn: 314429
* [SystemZ] Custom-expand ATOMIC_CMP_AND_SWAP_WITH_SUCCESSUlrich Weigand2017-09-284-22/+67
| | | | | | | | The SystemZ compare-and-swap instructions already provide the "success" indication via a condition-code value, so the default expansion of those operations generates an unnecessary extra comparsion. llvm-svn: 314428
* [dwarfdump] Verify that CUs have a unit DIE.Jonas Devlieghere2017-09-281-3/+8
| | | | | | | | | This patch adds a check to the DWARF verifier to detect CUs without a unit DIE. Differential revision: https://reviews.llvm.org/D38363 llvm-svn: 314426
* Use SDValue::getConstantOperandVal helper. NFCI.Simon Pilgrim2017-09-281-3/+3
| | | | llvm-svn: 314425
* [mips] Remove codegen support for branch likely instructions.Simon Dardis2017-09-282-18/+49
| | | | | | | | | | | | | | | | | | This patch disables codegen support for branch likely instructions to address a potential bug. These branches were unselectable as they had the same patterns as the normal branches but came after them when ISel was concerned. The branch likely instructions were marked as having no delay slots when they have annulling delay slots. The delay slot filler does not currently handle annulling delay slot branches, so this would lead to wrong codegen if these branches were generated. Reviewers: atanasyan, nitesh.jain Differential Revision: https://reviews.llvm.org/D38169 llvm-svn: 314421
* [LoopUnroll] Fix use after poison.Benjamin Kramer2017-09-281-1/+3
| | | | llvm-svn: 314418
* [DebugInfo] Do not extend range for physreg in LiveDebugVariablesBjorn Pettersson2017-09-281-6/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: A DBG_VALUE that is referring to a physical register is valid up until the next def of the register, or the end of the basic block that it belongs to. LiveDebugVariables is computing live intervals (slot index ranges) for DBG_VALUE instructions, before regalloc, in order to be able to re-insert DBG_VALUE instructions again after regalloc. When the DBG_VALUE is mapping a variable to a physical register we do not need to compute the range. We should simply re-insert the DBG_VALUE at the start position. The problem that was found, resulting in this patch, was a situation when the DBG_VALUE was the last real use of the physical register. The computeIntervals/extendDef methods extended the range to cover the whole basic block, even though the physical register very well could be allocated to some virtual register inside the basic block. So the extended range could not be trusted. This patch is a preparation for https://reviews.llvm.org/D38229, where the goal is to insert DBG_VALUE after each new definition of a variable, even if the virtual registers that the variable was connected to has been coalesced into using the same physical register (e.g. due to two address instructions). For more info see https://bugs.llvm.org/show_bug.cgi?id=34545 Reviewers: aprantl, rnk, echristo Reviewed By: aprantl Subscribers: Ka-Ka, llvm-commits Differential Revision: https://reviews.llvm.org/D38140 llvm-svn: 314414
* [LVI] Move LVILatticeVal class to separate header file (NFC).Florian Hahn2017-09-283-347/+160
| | | | | | | | | | | | | | | | | Summary: This allows sharing the lattice value code between LVI and SCCP (D36656). It also adds a `satisfiesPredicate` function, used by D36656. Reviewers: davide, sanjoy, efriedma Reviewed By: sanjoy Subscribers: mgorny, llvm-commits Differential Revision: https://reviews.llvm.org/D37591 llvm-svn: 314411
* [x86][AsmParser] Allow some more MS size directivesCoby Tayree2017-09-281-0/+3
| | | | | | | MS allows the following size directives: float/double and long as synonymous to dword/qword and dword, respectively. Differential Revision: https://reviews.llvm.org/D37190 llvm-svn: 314410
* Teach TargetInstrInfo::getInlineAsmLength to parse .space directives with ↵Alex Bradbury2017-09-283-55/+32
| | | | | | | | | | | | | | | | | | | | | | | | integer arguments It's currently quite difficult to test passes like branch relaxation, which requires branches with large displacement to be generated. The .space assembler directive makes it easy to create arbitrarily large basic blocks, but getInlineAsmLength is not able to parse it and so the size of the block is not correctly estimated. Other backends (AArch64, AMDGPU) introduce options just for testing that artificially restrict the ranges of branch instructions (e.g. aarch64-tbz-offset-bits). Although parsing a single form of the .space directive feels inelegant, it does allow a more direct testing approach. This patch adapts the .space parsing code from Mips16InstrInfo::getInlineAsmLength and removes it now the extra functionality is provided by the base implementation. I want to move this functionality to the generic getInlineAsmLength as 1) I need the same for RISC-V, and 2) I feel other backends will benefit from more direct testing of large branch displacements. Differential Revision: https://reviews.llvm.org/D37798 llvm-svn: 314393
* [PowerPC] eliminate partially redundant compare instructionHiroshi Inoue2017-09-281-14/+180
| | | | | | | | | | | | | | | | | | This is a follow-on of D37211. D37211 eliminates a compare instruction if two conditional branches can be made based on the one compare instruction, e.g. if (a == 0) { ... } else if (a < 0) { ... } This patch extends this optimization to support partially redundant cases, which often happen in while loops. For example, one compare instruction is moved from the loop body into the preheader by this optimization in the following example. do { if (a == 0) dummy1(); a = func(a); } while (a > 0); Differential Revision: https://reviews.llvm.org/D38236 llvm-svn: 314390
* [RISCV] Add common fixups and relocationsAlex Bradbury2017-09-2811-39/+593
| | | | | | | | | | | | | %lo(), %hi(), and %pcrel_hi() are supported and test cases have been added to ensure the appropriate fixups and relocations are generated. I've added an instruction format field which is used in RISCVMCCodeEmitter to, for instance, tell whether it should emit a lo12_i fixup or a lo12_s fixup (RISC-V has two 12-bit immediate encodings depending on the instruction type). Differential Revision: https://reviews.llvm.org/D23568 llvm-svn: 314389
* [RegAllocGreedy]: Allow recoloring of done register if it's non-tiedMikael Holmen2017-09-281-2/+14
| | | | | | | | | | | | | | | | | | | | | Summary: If we have a non-allocated register, we allow us to try recoloring of an already allocated and "Done" register, even if they are of the same register class, if the non-allocated register has at least one tied def and the allocated one has none. It should be easier to recolor the non-tied register than the tied one, so it might be an improvement even if they use the same regclasses. Reviewers: qcolombet Reviewed By: qcolombet Subscribers: llvm-commits, MatzeB Differential Revision: https://reviews.llvm.org/D38309 llvm-svn: 314388
* [DAGCombiner] Fix an off-by-one error in vector logicGeorge Burgess IV2017-09-281-2/+2
| | | | | | | | | Without this, we could end up trying to get the Nth (0-indexed) element from a subvector of size N. Differential Revision: https://reviews.llvm.org/D37880 llvm-svn: 314380
* bpf: add new insns for bswap_to_le and negationYonghong Song2017-09-283-14/+70
| | | | | | | | | | | | | | | | This patch adds new insn, "reg = be16/be32/be64 reg", for bswap to little endian for big-endian target (bpfeb). It also adds new insn for negation "reg = -reg". Currently, for source code, e.g., b = -a LLVM still prefers to generate: b = 0 - a But "reg = -reg" format can be used in assembly code. Signed-off-by: Yonghong Song <yhs@fb.com> Acked-by: Alexei Starovoitov <ast@kernel.org> llvm-svn: 314376
* Use a BumpPtrAllocator for Loop objectsSanjoy Das2017-09-2814-34/+55
| | | | | | | | | | | | | | | Summary: And now that we no longer have to explicitly free() the Loop instances, we can (with more ease) use the destructor of LoopBase to do what LoopBase::clear() was doing. Reviewers: chandlerc Subscribers: mehdi_amini, mcrosier, llvm-commits Differential Revision: https://reviews.llvm.org/D38201 llvm-svn: 314375
* Fix a UBsan bot.Rui Ueyama2017-09-281-0/+1
| | | | | | | | | If we do not initialize Prefix here, Prefix.data() returns a nullptr. Later, it is passed to memcpy. memcpy's behavior is undefined if src (or dst) is a nullptr even if a given size is 0. That's why this code triggered UBsan. llvm-svn: 314368
* [CodeGen] Fix some Clang-tidy modernize-use-default-member-init and Include ↵Eugene Zelenko2017-09-277-208/+284
| | | | | | What You Use warnings; other minor fixes (NFC). llvm-svn: 314363
* Reverted r313993.Galina Kistanova2017-09-271-15/+0
| | | | | | This patch produces a crash and hexagon_vector_loop_carried_reuse_constant.ll test fails on Windows (llvm-clang-x86_64-expensive-checks-win build bot). llvm-svn: 314361
* Revert r314017 '[InstCombine] Simplify check for RHS being a splat constant ↵Craig Topper2017-09-271-16/+22
| | | | | | | | in foldICmpUsingKnownBits by just checking Op1Min==Op1Max rather than going through m_APInt.' This reverts r314017 and similar code added in later commits. It seems to not work for pointer compares and is causing a bot failure for the last several days. llvm-svn: 314360
* Fix -Wunused-variable for Release build.Rui Ueyama2017-09-271-1/+1
| | | | llvm-svn: 314353
* Return the LoopUnrollResult from tryToUnrollLoop; NFCSanjoy Das2017-09-271-31/+22
| | | | | | I will use this in a later change. llvm-svn: 314352
* LoopDeletion: use return value instead of passing in LPMUpdater; NFCSanjoy Das2017-09-271-19/+28
| | | | | | I will use this refactoring in a later patch. llvm-svn: 314351
* Rename LoopUnrollStatus to LoopUnrollResult; NFCSanjoy Das2017-09-272-14/+14
| | | | | | A "Result" suffix is more appropriate here llvm-svn: 314350
* Fix off-by-one error in TarWriter.Rui Ueyama2017-09-271-26/+31
| | | | | | | | | | | | | | | | | | | | | | | | The tar format originally supported up to 99 byte filename. The two extensions are proposed later: Ustar or PAX. In the UStar extension, a pathanme is split at a '/' and its "prefix" and "suffix" are stored in different locations in the tar header. Since "prefix" can be up to 155 byte, it can represent up to 254 byte filename (but exact limit depends on the location of '/' character in a pathname.) Our TarWriter first attempt to use UStar extension and then fallback to PAX extension. But there's a bug in UStar header creation. "Suffix" part must be a NUL- terminated string, but we didn't handle it correctly. As a result, if your filename just 100 characters long, the last character was droppped. This patch fixes the issue. Differential Revision: https://reviews.llvm.org/D38149 llvm-svn: 314349
* Cleanup some problems with LLVM_ENABLE_DUMP in release builds, andDon Hinton2017-09-272-1/+2
| | | | | | | | always set LLVM_ENABLE_DUMP=ON for +Asserts builds. Differential Revision: https://reviews.llvm.org/D38306 llvm-svn: 314346
* Do not remove a target file in FileOutputBuffer::create().Rui Ueyama2017-09-271-8/+1
| | | | | | | | | | | | | | | | | | FileOutputBuffer::create() attempts to remove a target file if the file is a regular one, which results in an unexpected result in a failure scenario. If something goes wrong and the user of FileOutputBuffer decides to not call commit(), it leaves nothing. An existing file is removed, and no new file is created. What we should do is to atomically replace an existing file with a new file using rename(), so that it wouldn't remove an existing file without creating a new one. Differential Revision: https://reviews.llvm.org/D38283 llvm-svn: 314345
* [MachineOutliner] AArch64: Avoid saving + restoring LR if possibleJessica Paquette2017-09-275-167/+290
| | | | | | | | | | | | | | | | This commit allows the outliner to avoid saving and restoring the link register on AArch64 when it is dead within an entire class of candidates. This introduces changes to the way the outliner interfaces with the target. For example, the target now interfaces with the outliner using a MachineOutlinerInfo struct rather than by using getOutliningCallOverhead and getOutliningFrameOverhead. This also improves several comments on the outliner's cost model. https://reviews.llvm.org/D36721 llvm-svn: 314341
* Revert r314249 "Recommit r314151 "[X86] Make all the NOREX CodeGenOnly ↵Craig Topper2017-09-274-37/+27
| | | | | | | | instructions into postRA pseudos like the NOREX version of TEST.""" This caused PR34751 llvm-svn: 314339
* Revert r314248 "[X86] Don't emit X86::MOV8rr_NOREX from ↵Craig Topper2017-09-271-5/+7
| | | | | | | | X86InstrInfo::copyPhysReg." This contributed to PR34751 llvm-svn: 314338
* [X86][SSE] Pull out variable shuffle mask combine logic. NFCI.Simon Pilgrim2017-09-271-10/+13
| | | | | | Hopefully this will make it easier to vary the combine depth threshold per-target. llvm-svn: 314337
* [CodeGen] Emit necessary .note sections for -fsplit-stackThan McIntosh2017-09-273-1/+16
| | | | | | | | | | | | | | | | | | | | | Summary: According to https://gcc.gnu.org/wiki/SplitStacks, the linker expects a zero-sized .note.GNU-split-stack section if split-stack is used (and also .note.GNU-no-split-stack section if it also contains non-split-stack functions), so it can handle the cases where a split-stack function calls non-split-stack function. This change adds the sections if needed. Fixes PR #34670. Reviewers: thanm, rnk, luqmana Reviewed By: rnk Subscribers: llvm-commits Patch by Cherry Zhang <cherryyz@google.com> Differential Revision: https://reviews.llvm.org/D38051 llvm-svn: 314335
* [X86] Rewrite the zero vector checks in lowerV2X128VectorShuffle to use the ↵Craig Topper2017-09-271-23/+10
| | | | | | | | | | Zeroable APInt We already have zeroable bits in an APInt. We might as well use that instead of checking for an all zero BUILD_VECTOR. Differential Revision: https://reviews.llvm.org/D37950 llvm-svn: 314332
* [X86] In combineLoopSADPattern, pad result with zeros and use full size add ↵Craig Topper2017-09-271-10/+7
| | | | | | | | | | | | | | instead of using a smaller add and inserting. In some cases the result psadbw is smaller than the type of the add that started the match. Currently in these cases we are using a smaller add and inserting the result. If we instead combine the psadbw with zeros and use the full size add we can take advantage of implicit zeroing we get if we emit a narrower move before the add. In a future patch, I want to make isel aware that the psadbw itself already zeroed the upper bits and remove the move entirely. Differential Revision: https://reviews.llvm.org/D37453 llvm-svn: 314331
* [SLP] Fix crash on propagate IR flags for undef operands of min/maxAlexey Bataev2017-09-271-3/+6
| | | | | | | | | | | reductions. If both operands of the newly created SelectInst are Undefs the resulting operation is also Undef, not SelectInst. It may cause crashes when trying to propagate IR flags because function expects exactly SelectInst instruction, nothing else. llvm-svn: 314323
* [support] mapped_file_region: and fix the windows code tooRoman Lebedev2017-09-271-2/+2
| | | | | | | Followup for r314312 / r314313 Sorry, i really failed to fully grep all the codebase :/ llvm-svn: 314321
* [InstCombine] Gating select arithmetic optimization.Chad Rosier2017-09-271-2/+3
| | | | | | | | | | | | These changes faciliate positive behavior for arithmetic based select expressions that match its translation criteria, keeping code size gated to neutral or improved scenarios. Patch by Michael Berg <michael_c_berg@apple.com>! Differential Revision: https://reviews.llvm.org/D38263 llvm-svn: 314320
* [AArch64][Falkor] Ignore SP based loads in HW prefetch fixups.Geoff Berry2017-09-271-1/+6
| | | | | | | | | | Reviewers: mcrosier Subscribers: aemerson, rengolin, javed.absar, kristof.beyls Differential Revision: https://reviews.llvm.org/D38301 llvm-svn: 314319
* [SLP] fix typos/formatting; NFCSanjay Patel2017-09-271-14/+13
| | | | llvm-svn: 314315
* [Support] mapped_file_region::size() returns size_tRoman Lebedev2017-09-271-1/+1
| | | | | | Fixup last commit, found by clang-stage1-cmake-RA-incremental bot. llvm-svn: 314313
* [Support] mapped_file_region: store size as size_tRoman Lebedev2017-09-271-7/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: Found when testing stage-2 build with D38101. ``` In file included from /build/llvm/lib/Support/Path.cpp:1045: /build/llvm/lib/Support/Unix/Path.inc:648:14: error: comparison 'uint64_t' (aka 'unsigned long') > 18446744073709551615 is always false [-Werror,-Wtautological-constant-compare] if (length > std::numeric_limits<size_t>::max()) { ~~~~~~ ^ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ``` `size_t` is `uint64_t` here, apparently, thus any `uint64_t` value always fits into `size_t`. Initial patch was to use some preprocessor logic to not check if the size is known to fit at compile time. But Zachary Turner suggested using this approach. Reviewers: Bigcheese, rafael, zturner, mehdi_amini Reviewed by (via email): zturner Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D38132 llvm-svn: 314312
* [SimplifyCFG] add a struct to house optional folds (PR34603)Sanjay Patel2017-09-274-76/+67
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This was intended to be no-functional-change, but it's not - there's a test diff. So I thought I should stop here and post it as-is to see if this looks like what was expected based on the discussion in PR34603: https://bugs.llvm.org/show_bug.cgi?id=34603 Notes: 1. The test improvement occurs because the existing 'LateSimplifyCFG' marker is not carried through the recursive calls to 'SimplifyCFG()->SimplifyCFGOpt().run()->SimplifyCFG()'. The parameter isn't passed down, so we pick up the default value from the function signature after the first level. I assumed that was a bug, so I've passed 'Options' down in all of the 'SimplifyCFG' calls. 2. I split 'LateSimplifyCFG' into 2 bits: ConvertSwitchToLookupTable and KeepCanonicalLoops. This would theoretically allow us to differentiate the transforms controlled by those params independently. 3. We could stash the optional AssumptionCache pointer and 'LoopHeaders' pointer in the struct too. I just stopped here to minimize the diffs. 4. Similarly, I stopped short of messing with the pass manager layer. I have another question that could wait for the follow-up: why is the new pass manager creating the pass with LateSimplifyCFG set to true no matter where in the pipeline it's creating SimplifyCFG passes? // Create an early function pass manager to cleanup the output of the // frontend. EarlyFPM.addPass(SimplifyCFGPass()); --> /// \brief Construct a pass with the default thresholds /// and switch optimizations. SimplifyCFGPass::SimplifyCFGPass() : BonusInstThreshold(UserBonusInstThreshold), LateSimplifyCFG(true) {} <-- switches get converted to lookup tables and loops may not be in canonical form If this is unintended, then it's possible that the current behavior of dropping the 'LateSimplifyCFG' setting via recursion was masking this bug. Differential Revision: https://reviews.llvm.org/D38138 llvm-svn: 314308
* [InlineCost] add visitSelectInst()Haicheng Wu2017-09-271-0/+82
| | | | | | | | | | InlineCost can understand Select IR now. This patch finds free Select IRs and continue the propagation of SimplifiedValues, ConstantOffsetPtrs, and SROAArgValues. Differential Revision: https://reviews.llvm.org/D37198 llvm-svn: 314307
* Typo: const MCSchedModel SchedModel -> const MCSchedModel &SchedModelKrzysztof Parzyszek2017-09-271-1/+1
| | | | llvm-svn: 314301
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