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authorCraig Topper <craig.topper@intel.com>2017-09-27 18:36:45 +0000
committerCraig Topper <craig.topper@intel.com>2017-09-27 18:36:45 +0000
commit05f71dd0367195ed3cd319104d8efc9a9128e174 (patch)
treed5e18cd127935cd8cfb294637f18a47697ec9c6b /llvm/lib
parent102c333d9a5da87a34dbff8ea84c025db5fb5278 (diff)
downloadbcm5719-llvm-05f71dd0367195ed3cd319104d8efc9a9128e174.tar.gz
bcm5719-llvm-05f71dd0367195ed3cd319104d8efc9a9128e174.zip
[X86] In combineLoopSADPattern, pad result with zeros and use full size add instead of using a smaller add and inserting.
In some cases the result psadbw is smaller than the type of the add that started the match. Currently in these cases we are using a smaller add and inserting the result. If we instead combine the psadbw with zeros and use the full size add we can take advantage of implicit zeroing we get if we emit a narrower move before the add. In a future patch, I want to make isel aware that the psadbw itself already zeroed the upper bits and remove the move entirely. Differential Revision: https://reviews.llvm.org/D37453 llvm-svn: 314331
Diffstat (limited to 'llvm/lib')
-rw-r--r--llvm/lib/Target/X86/X86ISelLowering.cpp17
1 files changed, 7 insertions, 10 deletions
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp
index 0852765333d..1cd3af98dc9 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -35536,16 +35536,13 @@ static SDValue combineLoopSADPattern(SDNode *N, SelectionDAG &DAG,
Sad = DAG.getNode(ISD::TRUNCATE, DL, VT, Sad);
if (VT.getSizeInBits() > ResVT.getSizeInBits()) {
- // Update part of elements of the reduction vector. This is done by first
- // extracting a sub-vector from it, updating this sub-vector, and inserting
- // it back.
- SDValue SubPhi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, ResVT, Phi,
- DAG.getIntPtrConstant(0, DL));
- SDValue Res = DAG.getNode(ISD::ADD, DL, ResVT, Sad, SubPhi);
- return DAG.getNode(ISD::INSERT_SUBVECTOR, DL, VT, Phi, Res,
- DAG.getIntPtrConstant(0, DL));
- } else
- return DAG.getNode(ISD::ADD, DL, VT, Sad, Phi);
+ // Fill the upper elements with zero to match the add width.
+ SDValue Zero = DAG.getConstant(0, DL, VT);
+ Sad = DAG.getNode(ISD::INSERT_SUBVECTOR, DL, VT, Zero, Sad,
+ DAG.getIntPtrConstant(0, DL));
+ }
+
+ return DAG.getNode(ISD::ADD, DL, VT, Sad, Phi);
}
/// Convert vector increment or decrement to sub/add with an all-ones constant:
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