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* [GVNHoist] Fix non-deterministic sort order of PHIs for identical instructionsMandeep Singh Grang2017-10-301-1/+1
| | | | | | | | | | | | | | Summary: This fixes failure in Transforms/GVNHoist/hoist.ll uncovered by D39245. Reviewers: hiraditya, spop, dberlin Reviewed By: dberlin Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D39410 llvm-svn: 316949
* [SelectionDAG] Add VSELECT demanded elts support to computeKnownBits Simon Pilgrim2017-10-301-4/+4
| | | | llvm-svn: 316947
* [SelectionDAG] Add VSELECT support to computeKnownBits Simon Pilgrim2017-10-301-0/+1
| | | | llvm-svn: 316944
* [SelectionDAG] Add SELECT demanded elts support to ComputeNumSignBitsSimon Pilgrim2017-10-301-4/+5
| | | | llvm-svn: 316933
* [MC] Split out register def/use idx calls to make debugging simpler. NFCI.Simon Pilgrim2017-10-301-3/+4
| | | | llvm-svn: 316927
* [X86][AVX512] Adding a pattern for broadcastm intrinsic.Jina Nahias2017-10-301-0/+64
| | | | | | | Differential Revision: https://reviews.llvm.org/D38312 Change-Id: I71c8605a8e4c98013ef25289694afc5cfd46bb0b llvm-svn: 316921
* Move isDSOLocal check and add a comment.Rafael Espindola2017-10-301-2/+12
| | | | llvm-svn: 316920
* [PPC CodeGen] Fix the bitreverse.i64 intrinsic.Fangrui Song2017-10-301-71/+34
| | | | | | | | | | | | Summary: The two 32-bit words were swapped. Update a test omitted in reverted r316270. Reviewers: jtony, aaron.ballman Subscribers: nemanjai, kbarton Differential Revision: https://reviews.llvm.org/D39163 llvm-svn: 316916
* [X86] Make sure we don't create locked inc/dec instructions when the carry ↵Craig Topper2017-10-304-19/+84
| | | | | | | | | | | | | | | | | | | | | | | flag is being used. Summary: INC/DEC don't update the carry flag so we need to make sure we don't try to use it. This patch introduces new X86ISD opcodes for locked INC/DEC. Teaches lowerAtomicArithWithLOCK to emit these nodes if INC/DEC is not slow or the function is being optimized for size. An additional flag is added that allows the INC/DEC to be disabled if the caller determines that the carry flag is being requested. The test_sub_1_cmp_1_setcc_ugt test is currently showing this bug. The other test case changes are recovering cases that were regressed in r316860. This should fully fix PR35068 finishing the fix started in r316860. Reviewers: RKSimon, zvi, spatel Reviewed By: zvi Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D39411 llvm-svn: 316913
* [X86] Remove AVX512 early out from X86FastISel::X86SelectCmp.Craig Topper2017-10-301-3/+0
| | | | | | This shouldn't be needed anymore since i1 isn't a legal type. llvm-svn: 316912
* [AMDGPU] Emit metadata for hidden arguments for kernel enqueueYaxun Liu2017-10-302-4/+51
| | | | | | | | | | | | | Identifies kernels which performs device side kernel enqueues and emit metadata for the associated hidden kernel arguments. Such kernels are marked with calls-enqueue-kernel function attribute by AMDGPUOpenCLEnqueueKernelLowering pass and later on hidden kernel arguments metadata HiddenDefaultQueue and HiddenCompletionAction are emitted for them. Differential Revision: https://reviews.llvm.org/D39255 llvm-svn: 316907
* [CodeGen][ExpandMemcmp] Allow memcmp to expand to vector loads (2).Clement Courbet2017-10-307-38/+74
| | | | | | | | | | | | - Targets that want to support memcmp expansions now return the list of supported load sizes. - Expansion codegen does not assume that all power-of-two load sizes smaller than the max load size are valid. For examples, this is not the case for x86(32bit)+sse2. Fixes PR34887. llvm-svn: 316905
* [Hexagon] Allow the RDF optimizations to be run in .mir testcasesKrzysztof Parzyszek2017-10-302-5/+7
| | | | llvm-svn: 316904
* [GlobalISel|ARM] : Allow legalizing G_FSUBJaved Absar2017-10-303-8/+13
| | | | | | | | Adding support for VSUB. Reviewed by: @rovka Differential Revision: https://reviews.llvm.org/D39261 llvm-svn: 316902
* Invalid used of 'w' suffix on push and pop using 64-bit register.Andrew V. Tischenko2017-10-301-1/+3
| | | | | | Differential Revision: https://reviews.llvm.org/D38626 llvm-svn: 316898
* Revert "[X86][AVX512] Adding a pattern for broadcastm intrinsic."Jina Nahias2017-10-301-64/+0
| | | | | | | This reverts commit r316890. Change-Id: I683cceee9848ef309b452293086b1f26a941950d llvm-svn: 316894
* Recommit r315288: [SCCP] Propagate integer range info for parameters in IPSCCP.Florian Hahn2017-10-301-7/+95
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This version of the patch includes a fix addressing a stage2 LTO buildbot failure and addressed some additional nits. Original commit message: This updates the SCCP solver to use of the ValueElement lattice for parameters, which provides integer range information. The range information is used to remove unneeded icmp instructions. For the following function, f() can be optimized to ret i32 2 with this change source_filename = "sccp.c" target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128" target triple = "x86_64-unknown-linux-gnu" ; Function Attrs: norecurse nounwind readnone uwtable define i32 @main() local_unnamed_addr #0 { entry: %call = tail call fastcc i32 @f(i32 1) %call1 = tail call fastcc i32 @f(i32 47) %add3 = add nsw i32 %call, %call1 ret i32 %add3 } ; Function Attrs: noinline norecurse nounwind readnone uwtable define internal fastcc i32 @f(i32 %x) unnamed_addr #1 { entry: %c1 = icmp sle i32 %x, 100 %cmp = icmp sgt i32 %x, 300 %. = select i1 %cmp, i32 1, i32 2 ret i32 %. } attributes #1 = { noinline } Reviewers: davide, sanjoy, efriedma, dberlin Reviewed By: davide, dberlin Subscribers: mcrosier, gberry, mssimpso, dberlin, llvm-commits Differential Revision: https://reviews.llvm.org/D36656 llvm-svn: 316891
* [X86][AVX512] Adding a pattern for broadcastm intrinsic.Jina Nahias2017-10-301-0/+64
| | | | | | | Differential Revision: https://reviews.llvm.org/D38312 Change-Id: I6551fb13879e098aed74de410e29815cf37d9ab5 llvm-svn: 316890
* [IRCE][NFC] Store Length as SCEV in RangeCheck instead of ValueMax Kazantsev2017-10-301-6/+6
| | | | llvm-svn: 316889
* Revert r316887 to fix buildbot failures.Florian Hahn2017-10-301-93/+7
| | | | llvm-svn: 316888
* Recommit r315288: [SCCP] Propagate integer range info for parameters in IPSCCP.Florian Hahn2017-10-301-7/+93
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This version of the patch includes a fix addressing a stage2 LTO buildbot failure and addressed some additional nits. Original commit message: This updates the SCCP solver to use of the ValueElement lattice for parameters, which provides integer range information. The range information is used to remove unneeded icmp instructions. For the following function, f() can be optimized to ret i32 2 with this change source_filename = "sccp.c" target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128" target triple = "x86_64-unknown-linux-gnu" ; Function Attrs: norecurse nounwind readnone uwtable define i32 @main() local_unnamed_addr #0 { entry: %call = tail call fastcc i32 @f(i32 1) %call1 = tail call fastcc i32 @f(i32 47) %add3 = add nsw i32 %call, %call1 ret i32 %add3 } ; Function Attrs: noinline norecurse nounwind readnone uwtable define internal fastcc i32 @f(i32 %x) unnamed_addr #1 { entry: %c1 = icmp sle i32 %x, 100 %cmp = icmp sgt i32 %x, 300 %. = select i1 %cmp, i32 1, i32 2 ret i32 %. } attributes #1 = { noinline } Reviewers: davide, sanjoy, efriedma, dberlin Reviewed By: davide, dberlin Subscribers: mcrosier, gberry, mssimpso, dberlin, llvm-commits Differential Revision: https://reviews.llvm.org/D36656 llvm-svn: 316887
* [GVN][NFC] Mark instruction for deletion instead of immediate erasing in LoadPREMax Kazantsev2017-10-301-2/+1
| | | | | | | | It is done to uniformly handle instructions removal. Differential Revision: https://reviews.llvm.org/D39369 llvm-svn: 316884
* [X86] Rearrange code in X86InstrInfo.cpp to put all the ↵Craig Topper2017-10-301-270/+270
| | | | | | | | foldMemoryOperandImpl methods together without partial/undef register handling in the middle. NFC I have a future patch that wants to make use of the one of the partial functions in one of the earlier memory folding methods and the current ordering prevents that. llvm-svn: 316883
* [X86] Simplify code by removing an unnecessary temporary variable. NFCCraig Topper2017-10-301-2/+1
| | | | llvm-svn: 316882
* [X86] Move some EVEX->VEX code to a helper function to prepare for a future ↵Craig Topper2017-10-301-24/+33
| | | | | | patch. NFC llvm-svn: 316881
* [SelectionDAG] Add SEXT/AND/XOR/Or demanded elts support to ComputeNumSignBitsSimon Pilgrim2017-10-291-7/+11
| | | | llvm-svn: 316875
* [(new) Pass Manager] instantiate SimplifyCFG with the same options as the old PMSanjay Patel2017-10-291-2/+7
| | | | | | | | | | | | The old PM sets the options of what used to be known as "latesimplifycfg" on the instantiation after the vectorizers have run, so that's what we'redoing here. FWIW, there's a later SimplifyCFGPass instantiation in both PMs where we do not set the "late" options. I'm not sure if that's intentional or not. Differential Revision: https://reviews.llvm.org/D39407 llvm-svn: 316869
* [SelectionDAG] Add SRA/SHL demanded elts support to ComputeNumSignBitsSimon Pilgrim2017-10-291-3/+29
| | | | | | Introduce a isConstOrDemandedConstSplat helper function that can recognise a constant splat build vector for at least the demanded elts we care about. llvm-svn: 316866
* [X86] Remove combine that turns X86ISD::LSUB into X86ISD::LADD. Update ↵Craig Topper2017-10-292-29/+8
| | | | | | | | | | | | patterns that depended on this. If the carry flag is being used, this transformation isn't safe. This does prevent some test cases from using DEC now, but I'll try to look into that separately. Fixes PR35068. llvm-svn: 316860
* [X86] Fix typo in comment. NFCCraig Topper2017-10-291-1/+1
| | | | llvm-svn: 316859
* [X86] Use the extended vector register classes in fast isel with AVX512F/VL.Craig Topper2017-10-291-10/+10
| | | | llvm-svn: 316857
* [X86] Add AVX512 support to X86FastISel::X86SelectFPExt and ↵Craig Topper2017-10-291-4/+12
| | | | | | X86FastISel::X86SelectFPTrunc. llvm-svn: 316856
* [X86] Add AVX512 support to X86FastISel::X86MaterializeFPCraig Topper2017-10-291-2/+6
| | | | llvm-svn: 316853
* [X86] Remove invalid code from LowerVSELECT.Craig Topper2017-10-281-4/+0
| | | | | | | | This code attempted to say that v8i16/v16i16 VSELECT is legal if BWI and VLX are enabled, but the only way we could reach this point is if the condition was not a vXi1 type. Which means it really wasn't legal. We don't have any tests that exercise this code. So I'm hoping it wasn't really reachable. llvm-svn: 316851
* [SelectionDAG] Add support for INSERT_SUBVECTOR to computeKnownBitsSimon Pilgrim2017-10-281-0/+34
| | | | llvm-svn: 316847
* [X86][SSE] Combine 128-bit target shuffles to PACKSS/PACKUS.Simon Pilgrim2017-10-281-0/+10
| | | | llvm-svn: 316845
* [X86][SSE] Split off matchVectorShuffleWithPACK. NFCI.Simon Pilgrim2017-10-281-16/+41
| | | | | | Split matchVectorShuffleWithPACK from lowerVectorShuffleWithPACK so that we can reuse it for target shuffle combines llvm-svn: 316844
* [X86] Fix a mistake in the X86ISelDAGToDAG.cpp code for MUL8r/IMUL8r.Craig Topper2017-10-281-1/+1
| | | | | | I think this code is unreachable due to some promotions that occur elsewhere. I'll look into that to be sure, but for now I thought I should at least fix the obvious typo. llvm-svn: 316840
* [X86] Replace some default cases in X86SelectShift with llvm_unreachable.Craig Topper2017-10-281-3/+3
| | | | llvm-svn: 316839
* [SimplifyCFG] use pass options and remove the latesimplifycfg passSanjay Patel2017-10-286-83/+74
| | | | | | | | | | | | | | | | | This is no-functional-change-intended. This is repackaging the functionality of D30333 (defer switch-to-lookup-tables) and D35411 (defer folding unconditional branches) with pass parameters rather than a named "latesimplifycfg" pass. Now that we have individual options to control the functionality, we could decouple when these fire (but that's an independent patch if desired). The next planned step would be to add another option bit to disable the sinking transform mentioned in D38566. This should also make it clear that the new pass manager needs to be updated to limit simplifycfg in the same way as the old pass manager. Differential Revision: https://reviews.llvm.org/D38631 llvm-svn: 316835
* [X86][SSE] Rename truncateVectorCompareWithPACKSS to ↵Simon Pilgrim2017-10-281-12/+11
| | | | | | | | truncateVectorWithPACKSS. NFC. We no longer rely on the vector source being a comparison result, just have sufficient sign bits. llvm-svn: 316834
* [SelectionDAG] Support 'bit preserving' floating points bitcasts on ↵Simon Pilgrim2017-10-281-7/+15
| | | | | | | | | | | | computeKnownBits/ComputeNumSignBits For cases where we know the floating point representations match the bitcasted integer equivalent, allow bitcasting to these types. This is especially useful for the X86 floating point compare results which return all/zero bits but as a floating point type. Differential Revision: https://reviews.llvm.org/D39289 llvm-svn: 316831
* [X86] Remove unneeded MVT::i1 related code from fast isel.Craig Topper2017-10-281-10/+0
| | | | llvm-svn: 316825
* [ConstantFold] Fix a crash when folding a GEP that has vector indexHaicheng Wu2017-10-281-0/+3
| | | | | | | | | | LLVM crashes when factoring out an out-of-bound index into preceding dimension and the preceding dimension uses vector index. Simply bail out now when this case happens. Differential Revision: https://reviews.llvm.org/D38677 llvm-svn: 316824
* [PartialInlineLibCalls] Teach PartialInlineLibCalls to honor nobuiltin, ↵Craig Topper2017-10-281-6/+5
| | | | | | | | | | | | | | | | | | | | | | | properly check the function signature, and check TLI::has Summary: We shouldn't do this transformation if the function is marked nobuitlin. We were only checking that the return type is floating point, we really should be checking the argument types and argument count as well. This can be accomplished by using the other version of getLibFunc that takes the Function and not just the name. We should also be checking TLI::has since sqrtf is a macro on Windows. Fixes PR32559. Reviewers: hfinkel, spatel, davide, efriedma Reviewed By: davide, efriedma Subscribers: efriedma, llvm-commits, eraman Differential Revision: https://reviews.llvm.org/D39381 llvm-svn: 316819
* AMDGPU/GlobalISel: Mark 32-bit G_FADD as legalTom Stellard2017-10-271-0/+2
| | | | | | | | | | | | Reviewers: arsenm Reviewed By: arsenm Subscribers: kzhuravl, wdng, nhaehnle, yaxunl, rovka, kristof.beyls, igorb, dstuttard, tpr, t-tye, llvm-commits Differential Revision: https://reviews.llvm.org/D38439 llvm-svn: 316815
* [support] remove tautological comparison in Support/Windows/Path.incBob Haarman2017-10-271-4/+0
| | | | | | | | | | | | | | | | | Summary: The removed code checks that we are able to handle a 64-bit number, but the code we're calling takes two dwords (for a total of 64 bits), so this is always true. Reviewers: zturner, rnk, majnemer, compnerd Reviewed By: zturner Subscribers: amccarth, hiraditya, lebedev.ri, llvm-commits Differential Revision: https://reviews.llvm.org/D39263 llvm-svn: 316814
* Revert "Add support for writing 64-bit symbol tables for archives when ↵Jake Ehrlich2017-10-271-55/+9
| | | | | | | | offsets become too large for 32-bit" This reverts commit r316805. llvm-svn: 316813
* Add support for writing 64-bit symbol tables for archives when offsets ↵Jake Ehrlich2017-10-271-9/+55
| | | | | | | | | | | | | become too large for 32-bit This should fix https://bugs.llvm.org//show_bug.cgi?id=34189 This change makes it so that if writing a K_GNU style archive, you need to output a > 32-bit offset it should output in K_GNU64 style instead. Differential Revision: https://reviews.llvm.org/D36812 llvm-svn: 316805
* [Hexagon] Adjust patterns to reflect instruction selection preferencesKrzysztof Parzyszek2017-10-271-7/+30
| | | | llvm-svn: 316804
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