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* Disable hash verification of enums.Zachary Turner2016-07-062-1/+3
| | | | llvm-svn: 274639
* Prune RelocVisitor.h include to avoid including COFF.h from MCJIT.hReid Kleckner2016-07-064-0/+7
| | | | | | | This helps to mitigate the conflict between COFF.h and winnt.h, which is PR28399. llvm-svn: 274637
* fix typo; NFCSanjay Patel2016-07-061-1/+1
| | | | llvm-svn: 274636
* Revert "Emit CodeView type records for nested classes."Adrian McCarthy2016-07-062-29/+7
| | | | | | This reverts commit 256b29322c827a2d94da56468c936596f5509032. llvm-svn: 274632
* Emit CodeView type records for nested classes.Adrian McCarthy2016-07-062-7/+29
| | | | | | Differential Revision: http://reviews.llvm.org/D21939 llvm-svn: 274629
* [LV] Don't widen trivial induction variablesMatthew Simpson2016-07-061-8/+58
| | | | | | | | | | | | | | | | | | | | We currently always vectorize induction variables. However, if an induction variable is only used for counting loop iterations or computing addresses with getelementptr instructions, we don't need to do this. Vectorizing these trivial induction variables can create vector code that is difficult to simplify later on. This is especially true when the unroll factor is greater than one, and we create vector arithmetic when computing step vectors. With this patch, we check if an induction variable is only used for counting iterations or computing addresses, and if so, scalarize the arithmetic when computing step vectors instead. This allows for greater simplification. This patch addresses the suboptimal pointer arithmetic sequence seen in PR27881. Reference: https://llvm.org/bugs/show_bug.cgi?id=27881 Differential Revision: http://reviews.llvm.org/D21620 llvm-svn: 274627
* Re-commit of 274613.Elena Demikhovsky2016-07-063-42/+89
| | | | | | | The prev commit failed on compilation. A minor change in one pattern in lib/Target/X86/X86InstrAVX512.td fixes the failure. llvm-svn: 274626
* [ARM] Do not test for CPUs, use SubtargetFeatures. Also remove 2 flags.Diana Picus2016-07-064-14/+20
| | | | | | | | | | | | | | | This is a follow-up for r273544. The end goal is to get rid of the isSwift / isCortexXY / isWhatever methods. This commit also removes two command-line flags that weren't used in any of the tests: widen-vmovs and swift-partial-update-clearance. The former may be easily replaced with the mattr mechanism, but the latter may not (as it is a subtarget property, and not a proper feature). Differential Revision: http://reviews.llvm.org/D21797 llvm-svn: 274620
* [ARM] Do not test for CPUs, use SubtargetFeatures (Part 3). NFCIDiana Picus2016-07-065-7/+40
| | | | | | | | | | | This is a follow-up for r273544 and r273853. The end goal is to get rid of the isSwift / isCortexXY / isWhatever methods. This commit also marks them as obsolete. Differential Revision: http://reviews.llvm.org/D21796 llvm-svn: 274616
* Reverted 274613 due to compilation failue. Elena Demikhovsky2016-07-063-89/+42
| | | | llvm-svn: 274615
* AVX-512: Optimization for patterns with i1 scalar typeElena Demikhovsky2016-07-063-42/+89
| | | | | | | | | | | | | | The patch removes redundant kmov instructions (not all, we still have a lot of work here) and redundant "and" instructions after "setcc". I use "AssertZero" marker between X86ISD::SETCC node and "truncate" to eliminate extra "and $1" instruction. I also changed zext, aext and trunc patterns in the .td file. It allows to remove extra "kmov" instruictions. This patch fixes https://llvm.org/bugs/show_bug.cgi?id=28173. Fast ISEL mode is not supported correctly for AVX-512. ICMP/FCMP scalar instruction should return result in k-reg. It will be fixed in one of the next patches. I redirected handling of "cmp" to the DAG builder mode. (The code looks worse in one specific test case, but without this fix the new patch fails). Differential revision: http://reviews.llvm.org/D21956 llvm-svn: 274613
* AMDGPU: Fix return of non-void-returning shadersNicolai Haehnle2016-07-061-6/+4
| | | | | | | | | | | | | | | | | Summary: Since "AMDGPU: Fix verifier errors in SILowerControlFlow", the logic that ensures that a non-void-returning shader falls off the end of the last basic block was effectively disabled, since SI_RETURN is now used. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=96731 Reviewers: arsenm, tstellarAMD Subscribers: arsenm, kzhuravl, llvm-commits Differential Revision: http://reviews.llvm.org/D21975 llvm-svn: 274612
* Fix handling of forward unreachable but reverse-reachable blocks in ↵Daniel Berlin2016-07-061-2/+16
| | | | | | MemorySSA construction llvm-svn: 274606
* [CFLAA] Split out more things from CFLSteens. NFC.George Burgess IV2016-07-066-196/+322
| | | | | | | | | | | "More things" = StratifiedAttrs and various bits like interprocedural summaries. Patch by Jia Chen. Differential Revision: http://reviews.llvm.org/D21964 llvm-svn: 274592
* [CFLAA] Split the CFL graph out from CFLSteens. NFC.George Burgess IV2016-07-064-122/+157
| | | | | | | | Patch by Jia Chen. Differential Revision: http://reviews.llvm.org/D21963 llvm-svn: 274591
* [MSSA] Fix typo. NFC.George Burgess IV2016-07-061-1/+1
| | | | llvm-svn: 274590
* [CFLAA] Split into Anders+Steens analysis.George Burgess IV2016-07-069-73/+198
| | | | | | | | | | | | | | | | | | | | | StratifiedSets (as implemented) is very fast, but its accuracy is also limited. If we take a more aggressive andersens-like approach, we can be way more accurate, but we'll also end up being slower. So, we've decided to split CFLAA into CFLSteensAA and CFLAndersAA. Long-term, we want to end up in a place where CFLSteens is queried first; if it can provide an answer, great (since queries are basically map lookups). Otherwise, we'll fall back to CFLAnders, BasicAA, etc. This patch splits everything out so we can try to do something like that when we get a reasonable CFLAnders implementation. Patch by Jia Chen. Differential Revision: http://reviews.llvm.org/D21910 llvm-svn: 274589
* AArch64: try to fix optimized build failure.Tim Northover2016-07-051-1/+2
| | | | | | | | | I think the Ops filled out by Regex::match contain pointers into the temporary std::string returned by StringRef::upper. Its lifetime is extended by the call to match, but only until the end of that call (not to the uses of Ops later on). llvm-svn: 274586
* [X86][AVX2] Simplified BROADCAST combining to avoid repeated matching attemptsSimon Pilgrim2016-07-051-12/+9
| | | | llvm-svn: 274583
* Fix an ordering problem in r274431Manman Ren2016-07-051-1/+1
| | | | llvm-svn: 274582
* AMDGPU: Remove unnecessary string usage in AsmPrinterMatt Arsenault2016-07-052-38/+49
| | | | | | | | Registers are printed a lot, so don't create temporary std::strings. Using char instead of a string to an ostream saves a function call. llvm-svn: 274581
* [asan] Add a hidden option for Mach-O global metadata liveness trackingRyan Govostes2016-07-051-0/+10
| | | | llvm-svn: 274578
* AArch64: TableGenerate system instruction operands.Tim Northover2016-07-0510-1959/+1255
| | | | | | | | | | | | | | | | | | | | The way the named arguments for various system instructions are handled at the moment has a few problems: - Large-scale duplication between AArch64BaseInfo.h and AArch64BaseInfo.cpp - That weird Mapping class that I have no idea what I was on when I thought it was a good idea. - Searches are performed linearly through the entire list. - We print absolutely all registers in upper-case, even though some are canonically mixed case (SPSel for example). - The ARM ARM specifies sysregs in terms of 5 fields, but those are relegated to comments in our implementation, with a slightly opaque hex value indicating the canonical encoding LLVM will use. This adds a new TableGen backend to produce efficiently searchable tables, and switches AArch64 over to using that infrastructure. llvm-svn: 274576
* TableGen: promote "code" type from syntactic sugar.Tim Northover2016-07-052-2/+27
| | | | | | | It's being immediately converted to a "string", but being able to tell what type the field was originally can be useful in backends. llvm-svn: 274575
* Revert r259387: "AArch64: Implement missed conditional compare sequences."Balaram Makam2016-07-053-49/+4
| | | | | | | This reverts commit r259387 because it inserts illegal code after legalization in some backends where i64 OR type is illegal for example. llvm-svn: 274573
* [X86][AVX2] Add support for target shuffle combining to BROADCASTSimon Pilgrim2016-07-051-6/+20
| | | | | | Only support broadcast from vector register so far - memory folding support will have to wait. llvm-svn: 274572
* [X86][AVX512] Fixed decoding of permd/permpd variable mask shuffles + ↵Simon Pilgrim2016-07-053-7/+10
| | | | | | | | enabled them for target shuffle combining Corrected element mask masking to extract the bottom index bits (now matches the perm2 implementation but for unary inputs). llvm-svn: 274571
* ARM: fix `-mlong-calls` for WoASaleem Abdulrasool2016-07-051-1/+1
| | | | | | | | | Not all code-paths set the relocation model to static for Windows. This currently breaks on Windows ARM with `-mlong-calls` when built with clang. Loosen the assertion to what it was previously. We would ideally ensure that all the configuration sets Windows to static relocation model. llvm-svn: 274570
* DAGCombiner: Fold away vector extract of insert with the same indexMatt Arsenault2016-07-051-0/+8
| | | | | | | This only really matters when the index is non-constant since the constant case already gets taken care of by other combines. llvm-svn: 274569
* AArch64: use correct SDValue # when looking for bitfield placement.Tim Northover2016-07-051-2/+3
| | | | | | | | | | The other use really does only care about the SDNode (it checks the opcode against a whitelist), but bitFieldPlacement can be misled if the node produces multiple results. Patch by Ismail Badawi. llvm-svn: 274567
* AMDGPU: Fix folding SGPRs into madak/madmk src0Matt Arsenault2016-07-054-6/+26
| | | | | | | | | | Because of the special immediate operand, the constant bus is already used so SGPRs are never useful. r263212 changed the name of the immediate operand, which broke the verifier check for the restriction. llvm-svn: 274564
* [MC/Darwin] Fix a -Wmisleading-indentation warning, reported by GCC 6.Davide Italiano2016-07-051-2/+2
| | | | llvm-svn: 274563
* AMDGPU/SI: Remove address space query functions from AMDGPUDAGToDAGISelTom Stellard2016-07-053-156/+78
| | | | | | | | | | | | | | | Summary: These have been replaced with TableGen code (except for isConstantLoad, which is still used for R600). The queries were broken for cases where MemOperand was a PseudoSourceValue. Reviewers: arsenm Subscribers: arsenm, kzhuravl, llvm-commits Differential Revision: http://reviews.llvm.org/D21684 llvm-svn: 274561
* [LV] Refactor integer induction widening (NFC)Matthew Simpson2016-07-051-87/+86
| | | | | | | | | This patch also removes the SCEV variants of getStepVector() since they have no uses after the refactoring. Differential Revision: http://reviews.llvm.org/D21903 llvm-svn: 274558
* [AMDGPU] rename DS_1A1D_Off8_NORET to DS_1A2D_Off8_NORET as ds_write2xx use ↵Valery Pykhtin2016-07-052-5/+5
| | | | | | 2 source registers. NFC. llvm-svn: 274556
* [X86][AVX512] Remove vector BROADCAST builtins.Simon Pilgrim2016-07-051-34/+0
| | | | llvm-svn: 274555
* [LLVM][INTRINSICS] adding intrinsics of CLFLUSHOPTMichael Zuckerman2016-07-051-1/+1
| | | | | | Differential Revision: http://reviews.llvm.org/D21789 llvm-svn: 274553
* [AMDGPU] Assembler: Fix parsing error with floating-point literals passed to ↵Sam Kolton2016-07-051-6/+1
| | | | | | | | integer instructions Differential Revision: http://reviews.llvm.org/D21972 llvm-svn: 274551
* [X86][AVX512] Autoupgrade the BROADCAST intrinsicsSimon Pilgrim2016-07-051-1/+9
| | | | llvm-svn: 274550
* [mips][ias] Remove k_PhysReg since it's not possible to create an operand of ↵Daniel Sanders2016-07-051-20/+7
| | | | | | | | | | | | this kind. Reviewers: sdardis Subscribers: dsanders, sdardis, llvm-commits Differential Revision: http://reviews.llvm.org/D21986 llvm-svn: 274547
* [Thumb] Reapply r272251 with a fix for PR28348 (mk 2)James Molloy2016-07-051-1/+43
| | | | | | | | | | | | | | | | | | | | | | | | | The important thing I was missing was ensuring newly added constants were kept in topological order. Repositioning the node is correct if the constant is newly added (so it has no topological ordering) but wrong if it already existed - positioning it next in the worklist would break the topological ordering. Original commit message: [Thumb] Select a BIC instead of AND if the immediate can be encoded more optimally negated If an immediate is only used in an AND node, it is possible that the immediate can be more optimally materialized when negated. If this is the case, we can negate the immediate and use a BIC instead; int i(int a) { return a & 0xfffffeec; } Used to produce: ldr r1, [CONSTPOOL] ands r0, r1 CONSTPOOL: 0xfffffeec And now produces: movs r1, #255 adds r1, #20 ; Less costly immediate generation bics r0, r1 llvm-svn: 274543
* Revert r274536: [mips][ias] Don't break apart and reconstruct StringRef's ↵Daniel Sanders2016-07-051-4/+6
| | | | | | | | for k_Token. NFC. It turns out that MSVC requires this. llvm-svn: 274538
* [mips][ias] Don't break apart and reconstruct StringRef's for k_Token. NFC.Daniel Sanders2016-07-051-6/+4
| | | | llvm-svn: 274536
* [PowerPC] - Legalize vector types by widening instead of integer promotionNemanja Ivanovic2016-07-053-1/+100
| | | | | | | | | | | | | | | | | | | This patch corresponds to review: http://reviews.llvm.org/D20443 It changes the legalization strategy for illegal vector types from integer promotion to widening. This only applies for vectors with elements of width that is a multiple of a byte since we have hardware support for vectors with 1, 2, 3, 8 and 16 byte elements. Integer promotion for vectors is quite expensive on PPC due to the sequence of breaking apart the vector, extending the elements and reconstituting the vector. Two of these operations are expensive. This patch causes between minor and major improvements in performance on most benchmarks. There are very few benchmarks whose performance regresses. These regressions can be handled in a subsequent patch with a DAG combine (similar to how this patch handles int -> fp conversions of illegal vector types). llvm-svn: 274535
* Object: support empty UID/GID fieldsSaleem Abdulrasool2016-07-051-2/+8
| | | | | | | | | Normal archives do not have empty UID/GID fields. However, the Microsoft Import library format is a customized archive (it just uses an alternate symbol index format). When the import library is constructed by lib.exe, the UID and GID fields are left empty. Do not abort on such an input. llvm-svn: 274528
* AMDGPU/R600: Add PatFrags for selecting the correct vtx id for loadsTom Stellard2016-07-054-45/+65
| | | | | | | | | This moves of the r600 logic out of isGlobalLoad() and into the TableGen files. Differential Revision: http://reviews.llvm.org/D21710 llvm-svn: 274527
* [Support][Error] Make logAllUnhandledErrors take a Twine for the banner, ratherLang Hames2016-07-041-0/+9
| | | | | | than a const string&. llvm-svn: 274526
* [IR,X86] Remove some intrinsic prefixes earlier in the auto-upgrade code so ↵Craig Topper2016-07-041-214/+226
| | | | | | we can shorten the length of the comparison strings and avoid repeatedly comparing the common prefix. No functional change intended. llvm-svn: 274522
* AMDGPU/SI: Remove hack for selecting < 32-bit loads to MUBUF instructionsTom Stellard2016-07-043-15/+15
| | | | | | | | | | | | | | | Summary: The isGlobalLoad() query was returning true for constant address space loads with memory types less than 32-bits, which is wrong. This logic has been replaced with PatFrag in the TableGen files, to provide the same functionality. Reviewers: arsenm Subscribers: arsenm, kzhuravl, llvm-commits Differential Revision: http://reviews.llvm.org/D21696 llvm-svn: 274521
* [X86][AVX512] Add support for lowering shuffles to VSHUFPDSimon Pilgrim2016-07-041-0/+5
| | | | llvm-svn: 274520
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