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* [arm fast-isel] Minor cleanup. No functional change intended.Chad Rosier2012-12-171-10/+6
| | | | llvm-svn: 170379
* Prepare LLVM to fix PR14625, exposing a hook in MCContext to manage theChandler Carruth2012-12-172-3/+3
| | | | | | | | | | compilation directory. This defaults to the current working directory, just as it always has, but now an assembler can choose to override it with a custom directory. I've taught llvm-mc about this option and added a test case. llvm-svn: 170371
* Removed trailing whitespaceMichael Ilseman2012-12-171-22/+22
| | | | llvm-svn: 170367
* [arm fast-isel] Fast-isel only handles simple VTs, so make sure the necessaryChad Rosier2012-12-171-10/+20
| | | | | | checks are in place. Some minor cleanup as well. llvm-svn: 170360
* Fix another SROA crasher, PR14601.Chandler Carruth2012-12-171-1/+1
| | | | | | | | This was a silly oversight, we weren't pruning allocas which were used by variable-length memory intrinsics from the set that could be widened and promoted as integers. Fix that. llvm-svn: 170353
* Query section for whether it should be executable.Tim Northover2012-12-171-5/+3
| | | | llvm-svn: 170350
* Teach MachO which sections contain codeTim Northover2012-12-172-3/+3
| | | | llvm-svn: 170349
* [msan] Fix lint warning.Evgeniy Stepanov2012-12-171-1/+2
| | | | llvm-svn: 170347
* Add instruction encodings / disassembly support for l2r instructions.Richard Osborne2012-12-173-33/+112
| | | | llvm-svn: 170345
* R600: enable S_*N2_* instructionsTom Stellard2012-12-171-4/+4
| | | | | | | | | | | They seem to work fine. Patch by: Christian König Reviewed-by: Tom Stellard <thomas.stellard@amd.com> Tested-by: Michel Dänzer <michel.daenzer@amd.com> Signed-off-by: Christian König <deathsimple@vodafone.de> llvm-svn: 170343
* R600: BB operand support for SITom Stellard2012-12-174-4/+27
| | | | | | | | | Patch by: Christian König Reviewed-by: Tom Stellard <thomas.stellard@amd.com> Tested-by: Michel Dänzer <michel.daenzer@amd.com> Signed-off-by: Christian König <deathsimple@vodafone.de> llvm-svn: 170342
* R600: remove nonsense setPrefLoopAlignmentTom Stellard2012-12-171-1/+0
| | | | | | | | | | | | | The Align parameter is a power of two, so 16 results in 64K alignment. Additional to that even 16 byte alignment doesn't make any sense, so just remove it. Patch by: Christian König Reviewed-by: Tom Stellard <thomas.stellard@amd.com> Tested-by: Michel Dänzer <michel.daenzer@amd.com> Signed-off-by: Christian König <deathsimple@vodafone.de> llvm-svn: 170341
* Teach the rewriting of memcpy calls to support subvector copies.Chandler Carruth2012-12-171-40/+41
| | | | | | | | | | | | | | | | | | This also cleans up a bit of the memcpy call rewriting by sinking some irrelevant code further down and making the call-emitting code a bit more concrete. Previously, memcpy of a subvector would actually miscompile (!!!) the copy into a single vector element copy. I have no idea how this ever worked. =/ This is the memcpy half of PR14478 which we probably weren't noticing previously because it didn't actually assert. The rewrite relies on the newly refactored insert- and extractVector functions to do the heavy lifting, and those are the same as used for loads and stores which makes the test coverage a bit more meaningful here. llvm-svn: 170338
* Revert/correct some FastISel changes in r170104 (EVT->MVT forPatrik Hagglund2012-12-172-16/+25
| | | | | | | | | TargetLowering::getRegClassFor). Some isSimple() guards were missing, or getSimpleVT() were hoisted too far, resulting in asserts on valid LLVM assembly input. llvm-svn: 170336
* Optimize tree walking in markAliveBlocks.Evgeniy Stepanov2012-12-171-4/+3
| | | | | | | | Check whether a BB is known as reachable before adding it to the worklist. This way BB's with multiple predecessors are added to the list no more than once. llvm-svn: 170335
* Add instruction encodings for PEEK and ENDIN.Richard Osborne2012-12-171-8/+8
| | | | | | Previously these were marked with the wrong format. llvm-svn: 170334
* Fix a secondary bug I introduced while fixing the first part of PR14478.Chandler Carruth2012-12-171-6/+2
| | | | | | | | | | | | The first half of fixing this bug was actually in r170328, but was entirely coincidental. It did however get me to realize the nature of the bug, and adapt the test case to test more interesting behavior. In turn, that uncovered the rest of the bug which I've fixed here. This should fix two new asserts that showed up in the vectorize nightly tester. llvm-svn: 170333
* Fix parameter name in prototypes in XCoreDisassembler.Richard Osborne2012-12-171-3/+3
| | | | llvm-svn: 170332
* Hoist a convertValue call to the two paths where it is needed.Chandler Carruth2012-12-171-3/+4
| | | | | | | | I noticed this while looking at r170328. We only ever do a vector rewrite when the alloca *is* the vector type, so it's good to not paper over bugs here by doing a convertValue that isn't needed. llvm-svn: 170331
* Add instruction encodings / disassembly support for rus instructions.Richard Osborne2012-12-173-19/+104
| | | | llvm-svn: 170330
* Hoist the insertVector helper to be a static helper.Chandler Carruth2012-12-171-49/+62
| | | | | | | | | | | | | | | This will allow its use inside of memcpy rewriting as well. This routine is more complex than extractVector, and some of its uses are not 100% where I want them to be so there is still some work to do here. While this can technically change the output in some cases, it shouldn't be a change that matters -- IE, it can leave some dead code lying around that prior versions did not, etc. Yet another step in the refactorings leading up to the solution to the last component of PR14478. llvm-svn: 170328
* Add instruction encodings for ZEXT and SEXT.Richard Osborne2012-12-171-8/+8
| | | | | | Previously these were marked with the wrong format. llvm-svn: 170327
* Lift the extractVector helper all the way out to a static helper function.Chandler Carruth2012-12-171-30/+32
| | | | | | | | | | | | | | | | | The method helpers all implicitly act upon the alloca, and what we really want is a fully generic helper. Doing memcpy rewrites is more special than all other rewrites because we are at times rewriting instructions which touch pointers *other* than the alloca. As a consequence all of the helpers needed by memcpy rewriting of sub-vector copies will need to be generalized fully. Note that all of these helpers ({insert,extract}{Integer,Vector}) are woefully uncommented. I'm going to go back through and document them once I get the factoring correct. No functionality changed. llvm-svn: 170325
* Factor the vector load rewriting into a more generic form.Chandler Carruth2012-12-171-16/+27
| | | | | | | | | This makes it suitable for use in rewriting memcpy in the presence of subvector memcpy intrinsics. No functionality changed. llvm-svn: 170324
* Add instruction encodings / disassembly support for 2r instructions.Richard Osborne2012-12-173-70/+148
| | | | llvm-svn: 170323
* Add instruction encodings / disassembly support for 0r instructions.Richard Osborne2012-12-172-9/+12
| | | | llvm-svn: 170322
* Simplify assertion in XCoreInstPrinter.Richard Osborne2012-12-171-2/+3
| | | | llvm-svn: 170321
* Update comments to match recommended doxygen style.Richard Osborne2012-12-174-16/+17
| | | | llvm-svn: 170320
* Remove unnecessary include.Richard Osborne2012-12-171-1/+0
| | | | llvm-svn: 170319
* Remove EFLAGS from the BLSI/BLSMSK/BLSR patterns. The nodes created by DAG ↵Craig Topper2012-12-171-11/+11
| | | | | | combine don't contain an EFLAGS def. llvm-svn: 170308
* Simplify BMI ANDN matching to use patterns instead of a DAG combine. Also ↵Craig Topper2012-12-174-13/+16
| | | | | | add ANDN to isDefConvertible. llvm-svn: 170305
* Add rest of BMI/BMI2 instructions to the folding tables as well as popcnt ↵Craig Topper2012-12-171-1/+26
| | | | | | and lzcnt. llvm-svn: 170304
* Remove store forms of DEC/INC from isDefConvertible. Since they are stores ↵Craig Topper2012-12-171-6/+2
| | | | | | they don't have a register def. llvm-svn: 170303
* Fix the first part of PR14478: memset now works.Chandler Carruth2012-12-171-34/+68
| | | | | | | | | | | | | | | | | | | PR14478 highlights a serious problem in SROA that simply wasn't being exercised due to a lack of vector input code mixed with C-library function calls. Part of SROA was written carefully to handle subvector accesses via memset and memcpy, but the rewriter never grew support for this. Fixing it required refactoring the subvector access code in other parts of SROA so it could be shared, and then fixing the splat formation logic and using subvector insertion (this patch). The PR isn't quite fixed yet, as memcpy is still broken in the same way. I'm starting on that series of patches now. Hopefully this will be enough to bring the bullet benchmark back to life with the bb-vectorizer enabled, but that may require fixing memcpy as well. llvm-svn: 170301
* Extract the logic for inserting a subvector into a vector alloca.Chandler Carruth2012-12-171-38/+50
| | | | | | | No functionality changed. Another step of refactoring toward solving PR14487. llvm-svn: 170300
* Lift the integer splat computation into a helper function.Chandler Carruth2012-12-171-11/+28
| | | | | | | | No functionality changed. Refactoring leading up to the fix for PR14478 which requires some significant changes to the memset and memcpy rewriting. llvm-svn: 170299
* Add debug prints for when optimizeLoadInstr folds a load.Craig Topper2012-12-171-0/+6
| | | | llvm-svn: 170298
* Add instruction encodings and disassembly for 1r instructions.Richard Osborne2012-12-167-42/+113
| | | | llvm-svn: 170293
* Add XCore disassembler.Richard Osborne2012-12-167-2/+113
| | | | | | | | Currently there is no instruction encoding info and XCoreDisassembler::getInstruction() always returns Fail. I intend to add instruction encodings and tests in follow on commits. llvm-svn: 170292
* Remove invalid instruction encodings.Richard Osborne2012-12-161-18/+0
| | | | llvm-svn: 170291
* Mark anything deriving from PseudoInstXCore as a pseudo instruction.Richard Osborne2012-12-161-1/+3
| | | | llvm-svn: 170290
* Set instruction size correctly in XCoreInstrFormats.tdRichard Osborne2012-12-161-20/+21
| | | | llvm-svn: 170289
* Change XCoreAsmPrinter to lower MachineInstrs to MCInsts before emission.Richard Osborne2012-12-1614-27/+401
| | | | | | | This change adds XCoreMCInstLower to do the lowering to MCInst and XCoreInstPrinter to print the MCInsts. llvm-svn: 170288
* Replace ${:comment} with the comment symbol.Richard Osborne2012-12-161-6/+6
| | | | llvm-svn: 170286
* Declare class DwarfDebug before use instead of relying on a forward declarationDmitri Gribenko2012-12-161-0/+1
| | | | | | | | from some other unrelated header. Patch by Kai. llvm-svn: 170284
* MCPureStreamer.cpp: Try to fix build, pruning EmitDebugLabel().NAKAMURA Takumi2012-12-161-1/+0
| | | | llvm-svn: 170280
* This patch is needed to make c++ exceptions work for mips16.Reed Kotler2012-12-1611-4/+43
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Mips16 is really a processor decoding mode (ala thumb 1) and in the same program, mips16 and mips32 functions can exist and can call each other. If a jal type instruction encounters an address with the lower bit set, then the processor switches to mips16 mode (if it is not already in it). If the lower bit is not set, then it switches to mips32 mode. The linker knows which functions are mips16 and which are mips32. When relocation is performed on code labels, this lower order bit is set if the code label is a mips16 code label. In general this works just fine, however when creating exception handling tables and dwarf, there are cases where you don't want this lower order bit added in. This has been traditionally distinguished in gas assembly source by using a different syntax for the label. lab1: ; this will cause the lower order bit to be added lab2=. ; this will not cause the lower order bit to be added In some cases, it does not matter because in dwarf and debug tables the difference of two labels is used and in that case the lower order bits subtract each other out. To fix this, I have added to mcstreamer the notion of a debuglabel. The default is for label and debug label to be the same. So calling EmitLabel and EmitDebugLabel produce the same result. For various reasons, there is only one set of labels that needs to be modified for the mips exceptions to work. These are the "$eh_func_beginXXX" labels. Mips overrides the debug label suffix from ":" to "=." . This initial patch fixes exceptions. More changes most likely will be needed to DwarfCFException to make all of this work for actual debugging. These changes will be to emit debug labels in some places where a simple label is emitted now. Some historical discussion on this from gcc can be found at: http://gcc.gnu.org/ml/gcc-patches/2008-08/msg00623.html http://gcc.gnu.org/ml/gcc-patches/2008-11/msg01273.html llvm-svn: 170279
* X86: Add a couple of target-specific dag combines that turn VSELECTS into ↵Benjamin Kramer2012-12-154-18/+88
| | | | | | | | | | | psubus if possible. We match the pattern "x >= y ? x-y : 0" into "subus x, y" and two special cases if y is a constant. DAGCombiner canonicalizes those so we first have to undo the canonicalization for those cases. The pattern occurs in gzip when the loop vectorizer is enabled. Part of PR14613. llvm-svn: 170273
* Relax an overly aggressive assert to fix PR14572.Chandler Carruth2012-12-151-1/+1
| | | | | | The alloca width is based on the alloc size, not the type size. llvm-svn: 170270
* Make '-mtune=x86_64' assume fast unaligned memory accesses.Chandler Carruth2012-12-151-1/+2
| | | | | | | | | | | | | | Not all chips targeted by x86_64 have this feature, but a dramatically increasing number do. Specifying a chip-specific tuning parameter will continue to turn the feature on or off as appropriate for that particular chip, but the generic flag should try to achieve the best performance on the most widely available hardware. Today, the number of chips with fast UA access dwarfs those without in the x86-64 space. Note that this also brings LLVM's code generation for this '-march' flag more in line with that of modern GCCs. Reviewed by Dan Gohman. llvm-svn: 170269
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